Lines Matching refs:PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X307_QAHB_CDFE_RATE3_MIN_EYE_DLY_K2_E5
35543 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X307_QAHB_CDFE_RATE3_MIN_EYE_DLY_K2_E5 (0x7f<<0) // Minimum eye delay value for rate3 during dll calibration