Lines Matching refs:PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X225_K2_E5
35300 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X225_K2_E5 0x002b84UL //Access:RW DataWidth:0x8 // Multi Field Register.