Lines Matching refs:PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X147_AHB_CMU_PROG_MULT_REF_CLK_WAIT_O_K2_E5
29896 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X147_AHB_CMU_PROG_MULT_REF_CLK_WAIT_O_K2_E5 (0x7<<0) // wait multiplication factor for msm_cmu_databank