Lines Matching refs:PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_SV_E5

10097   #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_SV_E5                                                           (0x1<<0) // ACS source validation.  Hardwired to 0 for upstream port.  Writable through PEM()_CFG_WR. However, the application must not change this field.