Lines Matching refs:PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT3_PL_STAT_E5
2802 #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT3_PL_STAT_E5 (0xff<<24) // Margin payload (status) for this lane.