Lines Matching refs:PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT12_PL_STAT_E5
3049 #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT12_PL_STAT_E5 (0xff<<24) // Margin payload (status) for this lane.