Lines Matching refs:MSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_STRICT_SRC_E5

89110   #define MSEM_REG_PASSIVE_BUFFER_WRITE_WRR_ARBITER_PB_WR_STRICT_SRC_E5                                      (0x7<<16) // This register defines if one of the source of the PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B, 100 - SDM.