Lines Matching refs:MCP_REG_SMBUS_EVENT_STATUS_MASTER_RX_FIFO_FULL
72507 #define MCP_REG_SMBUS_EVENT_STATUS_MASTER_RX_FIFO_FULL (0x1<<31) // This bit is set when the master receive FIFO become full. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.