Lines Matching refs:BMB_REG_INT_STS_9
63302 #define BMB_REG_INT_STS_9 0x54019cUL //Access:R DataWidth:0x20 // Multi Field Register.
63378 #define BMB_REG_INT_MASK_9_WC9_QUEUE_FIFO_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_QUEUE_FIFO_ERROR .
63380 #define BMB_REG_INT_MASK_9_WC9_FREE_POINT_FIFO_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_FREE_POINT_FIFO_ERROR .
63382 #define BMB_REG_INT_MASK_9_WC9_NEXT_POINT_FIFO_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_NEXT_POINT_FIFO_ERROR .
63384 #define BMB_REG_INT_MASK_9_WC9_STRT_FIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_STRT_FIFO_ERROR .
63386 #define BMB_REG_INT_MASK_9_WC9_SECOND_DSCR_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_SECOND_DSCR_FIFO_ERROR .
63388 #define BMB_REG_INT_MASK_9_WC9_PKT_AVAIL_FIFO_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_PKT_AVAIL_FIFO_ERROR .
63390 #define BMB_REG_INT_MASK_9_WC9_COS_CNT_FIFO_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_COS_CNT_FIFO_ERROR .
63392 #define BMB_REG_INT_MASK_9_WC9_NOTIFY_FIFO_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_NOTIFY_FIFO_ERROR .
63394 #define BMB_REG_INT_MASK_9_WC9_LL_REQ_FIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_LL_REQ_FIFO_ERROR .
63396 #define BMB_REG_INT_MASK_9_WC9_LL_PA_CNT_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_LL_PA_CNT_ERROR .
63398 #define BMB_REG_INT_MASK_9_WC9_BB_PA_CNT_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_BB_PA_CNT_ERROR .
63400 #define BMB_REG_INT_MASK_9_RC2_SOP_RC_OUT_SYNC_FIFO_ERROR_E5 (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC2_SOP_RC_OUT_SYNC_FIFO_ERROR .
63402 #define BMB_REG_INT_MASK_9_RC2_SOP_OUT_SYNC_FIFO_PUSH_ERROR_E5 (0x1<<12) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC2_SOP_OUT_SYNC_FIFO_PUSH_ERROR .
63404 #define BMB_REG_INT_MASK_9_RC0_SOP_PEND_FIFO_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC0_SOP_PEND_FIFO_ERROR .
63406 #define BMB_REG_INT_MASK_9_RC1_SOP_PEND_FIFO_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC1_SOP_PEND_FIFO_ERROR .
63408 #define BMB_REG_INT_MASK_9_RC2_SOP_PEND_FIFO_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC2_SOP_PEND_FIFO_ERROR .
63410 #define BMB_REG_INT_MASK_9_RC3_SOP_PEND_FIFO_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC3_SOP_PEND_FIFO_ERROR .
63412 #define BMB_REG_INT_MASK_9_RC4_SOP_PEND_FIFO_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC4_SOP_PEND_FIFO_ERROR .
63414 #define BMB_REG_INT_MASK_9_RC5_SOP_PEND_FIFO_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC5_SOP_PEND_FIFO_ERROR .
63416 #define BMB_REG_INT_MASK_9_RC6_SOP_PEND_FIFO_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC6_SOP_PEND_FIFO_ERROR .
63418 #define BMB_REG_INT_MASK_9_RC7_SOP_PEND_FIFO_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC7_SOP_PEND_FIFO_ERROR .
63420 #define BMB_REG_INT_MASK_9_RC0_DSCR_PEND_FIFO_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC0_DSCR_PEND_FIFO_ERROR .
63422 #define BMB_REG_INT_MASK_9_RC1_DSCR_PEND_FIFO_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC1_DSCR_PEND_FIFO_ERROR .
63424 #define BMB_REG_INT_MASK_9_RC2_DSCR_PEND_FIFO_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC2_DSCR_PEND_FIFO_ERROR .
63426 #define BMB_REG_INT_MASK_9_RC3_DSCR_PEND_FIFO_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC3_DSCR_PEND_FIFO_ERROR .
63428 #define BMB_REG_INT_MASK_9_RC4_DSCR_PEND_FIFO_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC4_DSCR_PEND_FIFO_ERROR .
63430 #define BMB_REG_INT_MASK_9_RC5_DSCR_PEND_FIFO_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC5_DSCR_PEND_FIFO_ERROR .
63432 #define BMB_REG_INT_MASK_9_RC6_DSCR_PEND_FIFO_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC6_DSCR_PEND_FIFO_ERROR .
63434 #define BMB_REG_INT_MASK_9_RC7_DSCR_PEND_FIFO_ERROR (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC7_DSCR_PEND_FIFO_ERROR .
63436 #define BMB_REG_INT_MASK_9_RC1_SOP_INP_SYNC_FIFO_PUSH_ERROR_E5 (0x1<<29) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC1_SOP_INP_SYNC_FIFO_PUSH_ERROR .
63438 #define BMB_REG_INT_MASK_9_RC2_SOP_INP_SYNC_FIFO_PUSH_ERROR_E5 (0x1<<30) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC2_SOP_INP_SYNC_FIFO_PUSH_ERROR .
63440 #define BMB_REG_INT_MASK_9_RC1_SOP_OUT_SYNC_FIFO_PUSH_ERROR_E5 (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC1_SOP_OUT_SYNC_FIFO_PUSH_ERROR .
63442 #define BMB_REG_INT_MASK_9_RC9_SOP_RC_OUT_SYNC_FIFO_ERROR_BB_K2 (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC9_SOP_RC_OUT_SYNC_FIFO_ERROR .
63444 #define BMB_REG_INT_MASK_9_RC9_SOP_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2 (0x1<<12) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC9_SOP_OUT_SYNC_FIFO_PUSH_ERROR .
63446 #define BMB_REG_INT_MASK_9_RC8_SOP_INP_SYNC_FIFO_PUSH_ERROR_BB_K2 (0x1<<29) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC8_SOP_INP_SYNC_FIFO_PUSH_ERROR .
63448 #define BMB_REG_INT_MASK_9_RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR_BB_K2 (0x1<<30) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR .
63450 #define BMB_REG_INT_MASK_9_RC8_SOP_OUT_SYNC_FIFO_PUSH_ERROR_BB_K2 (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC8_SOP_OUT_SYNC_FIFO_PUSH_ERROR .