Lines Matching defs:NWS_REG_DBG_FORCE_VALID_K2_E5

66881 #define NWS_REG_DBG_FORCE_VALID_K2_E5                                                                        0x700134UL //Access:RW   DataWidth:0x4    // DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).