Lines Matching refs:__BIT
65 #define __BIT(__n) \
69 ((__BIT(MAX((__m), (__n)) + 1) - 1) ^ (__BIT(MIN((__m), (__n))) - 1))
113 #define FUSECTL_MASK __BIT(31)
116 #define LEGFUSE_ACCEL_MASK_CIPHER_SLICE __BIT(0)
117 #define LEGFUSE_ACCEL_MASK_AUTH_SLICE __BIT(1)
118 #define LEGFUSE_ACCEL_MASK_PKE_SLICE __BIT(2)
119 #define LEGFUSE_ACCEL_MASK_COMPRESS_SLICE __BIT(3)
120 #define LEGFUSE_ACCEL_MASK_LZS_SLICE __BIT(4)
121 #define LEGFUSE_ACCEL_MASK_EIA3_SLICE __BIT(5)
122 #define LEGFUSE_ACCEL_MASK_SHA3_SLICE __BIT(6)
166 #define ETR_RING_CONFIG_LATE_HEAD_POINTER_MODE __BIT(31)
239 #define ETR_INT_COL_CTL_ENABLE __BIT(31)
245 #define ETR_AP_DEST_ENABLE __BIT(7)
294 #define FCU_STATUS_AUTHFWLD __BIT(8)
295 #define FCU_STATUS_DONE __BIT(9)
310 #define CAP_GLOBAL_CTL_MISC_TIMESTAMP_EN __BIT(7)
330 #define USTORE_ADDRESS_ECS __BIT(31)
354 #define CTX_ENABLES_INUSE_CONTEXTS __BIT(31)
355 #define CTX_ENABLES_CNTL_STORE_PARITY_ERROR __BIT(29)
356 #define CTX_ENABLES_CNTL_STORE_PARITY_ENABLE __BIT(28)
357 #define CTX_ENABLES_BREAKPOINT __BIT(27)
358 #define CTX_ENABLES_PAR_ERR __BIT(25)
359 #define CTX_ENABLES_NN_MODE __BIT(20)
360 #define CTX_ENABLES_NN_RING_EMPTY __BIT(18)
361 #define CTX_ENABLES_LMADDR_1_GLOBAL __BIT(17)
362 #define CTX_ENABLES_LMADDR_0_GLOBAL __BIT(16)
388 #define ACTIVE_CTX_STATUS_ABO __BIT(31)
458 #define AE_MISC_CONTROL_PARITY_ENABLE __BIT(24)
459 #define AE_MISC_CONTROL_FORCE_BAD_PARITY __BIT(23)
460 #define AE_MISC_CONTROL_ONE_CTX_RELOAD __BIT(22)
462 #define AE_MISC_CONTROL_SHARE_CS __BIT(2)
482 #define INTSTATSSM_SHANGERR __BIT(13)
489 #define SLICE_HANG_AUTH0_MASK __BIT(0)
490 #define SLICE_HANG_AUTH1_MASK __BIT(1)
491 #define SLICE_HANG_CPHR0_MASK __BIT(4)
492 #define SLICE_HANG_CPHR1_MASK __BIT(5)
493 #define SLICE_HANG_CMP0_MASK __BIT(8)
494 #define SLICE_HANG_CMP1_MASK __BIT(9)
495 #define SLICE_HANG_XLT0_MASK __BIT(12)
496 #define SLICE_HANG_XLT1_MASK __BIT(13)
497 #define SLICE_HANG_MMP0_MASK __BIT(16)
498 #define SLICE_HANG_MMP1_MASK __BIT(17)
499 #define SLICE_HANG_MMP2_MASK __BIT(18)
500 #define SLICE_HANG_MMP3_MASK __BIT(19)
501 #define SLICE_HANG_MMP4_MASK __BIT(20)
526 #define EMSK3_CPM0_MASK __BIT(2)
527 #define EMSK3_CPM1_MASK __BIT(3)
528 #define EMSK5_CPM2_MASK __BIT(16)
529 #define EMSK5_CPM3_MASK __BIT(17)
530 #define EMSK5_CPM4_MASK __BIT(18)
981 #define AE_MODE_RELOAD_CTX_SHARED __BIT(12)
982 #define AE_MODE_SHARED_USTORE __BIT(11)
983 #define AE_MODE_LMEM1 __BIT(9)
984 #define AE_MODE_LMEM0 __BIT(8)
1365 #define HW_AUTH_CONFIG_SHA3_PADDING __BIT(16)
1474 #define CIPHER_CONFIG_CONVERT __BIT(9)
1475 #define CIPHER_CONFIG_DIR __BIT(8)