Lines Matching defs:__BITS
68 #define __BITS(__m, __n) \
167 #define ETR_RING_CONFIG_NEAR_FULL_WM __BITS(14, 10)
168 #define ETR_RING_CONFIG_NEAR_EMPTY_WM __BITS(9, 5)
169 #define ETR_RING_CONFIG_RING_SIZE __BITS(4, 0)
246 #define ETR_AP_DEST_AE __BITS(6, 2)
247 #define ETR_AP_DEST_MAILBOX __BITS(1, 0)
284 #define FCU_CTRL_AE __BITS(8, 31)
287 #define FCU_STATUS_STS __BITS(0, 2)
296 #define FCU_STATUS_LOADED_AE __BITS(22, 31)
312 #define CAP_GLOBAL_CTL_RESET_MASK __BITS(31, 26)
313 #define CAP_GLOBAL_CTL_RESET_ACCEL_MASK __BITS(25, 20)
314 #define CAP_GLOBAL_CTL_RESET_AE_MASK __BITS(19, 0)
316 #define CAP_GLOBAL_CTL_CLK_EN_ACCEL_MASK __BITS(25, 20)
317 #define CAP_GLOBAL_CTL_CLK_EN_AE_MASK __BITS(19, 0)
324 #define AE_LOCAL_AE_MASK __BITS(31, 12)
325 #define AE_LOCAL_CSR_MASK __BITS(9, 0)
363 #define CTX_ENABLES_ENABLE __BITS(15,8)
379 #define CSR_CTX_POINTER_CONTEXT __BITS(2,0)
389 #define ACTIVE_CTX_STATUS_ACNO __BITS(0, 2)
461 #define AE_MISC_CONTROL_CS_RELOAD __BITS(21, 20)
472 #define AE_XFER_AE_MASK __BITS(31, 12)
473 #define AE_XFER_CSR_MASK __BITS(9, 2)
985 #define AE_MODE_NN_MODE __BITS(7, 4)
986 #define AE_MODE_CTX_MODE __BITS(3, 0)
1364 #define HW_AUTH_CONFIG_SHA3_ALGO __BITS(22, 23)
1366 #define HW_AUTH_CONFIG_CMPLEN __BITS(14, 8)
1368 #define HW_AUTH_CONFIG_MODE __BITS(7, 4)
1369 #define HW_AUTH_CONFIG_ALGO __BITS(3, 0)
1476 #define CIPHER_CONFIG_MODE __BITS(7, 4)
1477 #define CIPHER_CONFIG_ALGO __BITS(3, 0)