Lines Matching refs:cc
282 uint32_t cc;
287 cc = nvme_mmio_read_4(ctrlr, cc);
290 en = (cc >> NVME_CC_REG_EN_SHIFT) & NVME_CC_REG_EN_MASK;
314 cc &= ~NVME_CC_REG_EN_MASK;
315 nvme_mmio_write_4(ctrlr, cc, cc);
329 uint32_t cc;
336 cc = nvme_mmio_read_4(ctrlr, cc);
339 en = (cc >> NVME_CC_REG_EN_SHIFT) & NVME_CC_REG_EN_MASK;
372 cc = 0;
373 cc |= 1 << NVME_CC_REG_EN_SHIFT;
374 cc |= 0 << NVME_CC_REG_CSS_SHIFT;
375 cc |= 0 << NVME_CC_REG_AMS_SHIFT;
376 cc |= 0 << NVME_CC_REG_SHN_SHIFT;
377 cc |= 6 << NVME_CC_REG_IOSQES_SHIFT; /* SQ entry size == 64 == 2^6 */
378 cc |= 4 << NVME_CC_REG_IOCQES_SHIFT; /* CQ entry size == 16 == 2^4 */
381 cc |= (PAGE_SIZE >> 13) << NVME_CC_REG_MPS_SHIFT;
383 nvme_mmio_write_4(ctrlr, cc, cc);
1128 * Reset controller twice to ensure we do a transition from cc.en==1 to
1129 * cc.en==0. This is because we don't really know what status the
1538 uint32_t cc;
1542 cc = nvme_mmio_read_4(ctrlr, cc);
1543 cc &= ~(NVME_CC_REG_SHN_MASK << NVME_CC_REG_SHN_SHIFT);
1544 cc |= NVME_SHN_NORMAL << NVME_CC_REG_SHN_SHIFT;
1545 nvme_mmio_write_4(ctrlr, cc, cc);