Lines Matching refs:ntb
79 #include "dev/ntb/ntb.h"
133 device_printf(ntb->device, __VA_ARGS__); \
162 struct amd_ntb_softc *ntb = device_get_softc(dev);
164 amd_ntb_printf(1, "%s: conn_type %d\n", __func__, ntb->conn_type);
166 switch (ntb->conn_type) {
181 struct amd_ntb_softc *ntb = device_get_softc(dev);
190 struct amd_ntb_softc *ntb = device_get_softc(dev);
193 __func__, pidx, ntb->conn_type);
198 switch (ntb->conn_type) {
213 struct amd_ntb_softc *ntb = device_get_softc(dev);
231 amd_link_is_up(struct amd_ntb_softc *ntb)
235 __func__, ntb->peer_sta, ntb->cntl_sta);
237 if (!ntb->peer_sta)
238 return (NTB_LNK_STA_ACTIVE(ntb->cntl_sta));
244 amd_ntb_link_sta_speed(struct amd_ntb_softc *ntb)
247 if (!amd_link_is_up(ntb))
250 return (NTB_LNK_STA_SPEED(ntb->lnk_sta));
254 amd_ntb_link_sta_width(struct amd_ntb_softc *ntb)
257 if (!amd_link_is_up(ntb))
260 return (NTB_LNK_STA_WIDTH(ntb->lnk_sta));
266 struct amd_ntb_softc *ntb = device_get_softc(dev);
269 *speed = amd_ntb_link_sta_speed(ntb);
271 *width = amd_ntb_link_sta_width(ntb);
273 return (amd_link_is_up(ntb));
280 struct amd_ntb_softc *ntb = device_get_softc(dev);
284 __func__, ntb->int_mask, ntb->conn_type);
286 amd_init_side_info(ntb);
289 ntb->int_mask &= ~AMD_EVENT_INTMASK;
290 amd_ntb_reg_write(4, AMD_INTMASK_OFFSET, ntb->int_mask);
292 if (ntb->conn_type == NTB_CONN_SEC)
308 struct amd_ntb_softc *ntb = device_get_softc(dev);
312 __func__, ntb->int_mask, ntb->conn_type);
314 amd_deinit_side_info(ntb);
317 ntb->int_mask |= AMD_EVENT_INTMASK;
318 amd_ntb_reg_write(4, AMD_INTMASK_OFFSET, ntb->int_mask);
320 if (ntb->conn_type == NTB_CONN_SEC)
339 struct amd_ntb_softc *ntb = device_get_softc(dev);
341 return (ntb->hw_info->mw_count);
349 struct amd_ntb_softc *ntb = device_get_softc(dev);
352 if (mw_idx < 0 || mw_idx >= ntb->hw_info->mw_count)
355 bar_info = &ntb->bar_info[ntb->hw_info->bar_start_idx + mw_idx];
378 if ((mw_idx == 0) && (ntb->hw_info->quirks & QUIRK_MW0_32BIT))
390 struct amd_ntb_softc *ntb = device_get_softc(dev);
393 if (mw_idx < 0 || mw_idx >= ntb->hw_info->mw_count)
396 bar_info = &ntb->bar_info[ntb->hw_info->bar_start_idx + mw_idx];
427 if ((mw_idx == 0) && (ntb->hw_info->quirks & QUIRK_MW0_32BIT)) {
447 struct amd_ntb_softc *ntb = device_get_softc(dev);
451 if (mw_idx < 0 || mw_idx >= ntb->hw_info->mw_count)
460 struct amd_ntb_softc *ntb = device_get_softc(dev);
464 if (mw_idx < 0 || mw_idx >= ntb->hw_info->mw_count)
467 bar_info = &ntb->bar_info[ntb->hw_info->bar_start_idx + mw_idx];
481 struct amd_ntb_softc *ntb = device_get_softc(dev);
486 if (mw_idx < 0 || mw_idx >= ntb->hw_info->mw_count)
489 bar_info = &ntb->bar_info[ntb->hw_info->bar_start_idx + mw_idx];
501 struct amd_ntb_softc *ntb = device_get_softc(dev);
504 ntb->hw_info->db_count);
506 return (ntb->hw_info->db_count);
512 struct amd_ntb_softc *ntb = device_get_softc(dev);
515 __func__, ntb->db_valid_mask);
517 return (ntb->db_valid_mask);
523 struct amd_ntb_softc *ntb = device_get_softc(dev);
526 __func__, vector, ntb->hw_info->db_count, ntb->db_valid_mask);
528 if (vector < 0 || vector >= ntb->hw_info->db_count)
531 return (ntb->db_valid_mask & (1 << vector));
537 struct amd_ntb_softc *ntb = device_get_softc(dev);
550 struct amd_ntb_softc *ntb = device_get_softc(dev);
559 struct amd_ntb_softc *ntb = device_get_softc(dev);
561 DB_MASK_LOCK(ntb);
563 __func__, ntb->db_mask, db_bits);
565 ntb->db_mask |= db_bits;
566 amd_ntb_reg_write(2, AMD_DBMASK_OFFSET, ntb->db_mask);
567 DB_MASK_UNLOCK(ntb);
573 struct amd_ntb_softc *ntb = device_get_softc(dev);
575 DB_MASK_LOCK(ntb);
577 __func__, ntb->db_mask, db_bits);
579 ntb->db_mask &= ~db_bits;
580 amd_ntb_reg_write(2, AMD_DBMASK_OFFSET, ntb->db_mask);
581 DB_MASK_UNLOCK(ntb);
587 struct amd_ntb_softc *ntb = device_get_softc(dev);
599 struct amd_ntb_softc *ntb = device_get_softc(dev);
602 ntb->spad_count);
604 return (ntb->spad_count);
610 struct amd_ntb_softc *ntb = device_get_softc(dev);
615 if (idx < 0 || idx >= ntb->spad_count)
618 offset = ntb->self_spad + (idx << 2);
628 struct amd_ntb_softc *ntb = device_get_softc(dev);
633 if (idx < 0 || idx >= ntb->spad_count)
636 offset = ntb->self_spad + (idx << 2);
644 amd_ntb_spad_clear(struct amd_ntb_softc *ntb)
648 for (i = 0; i < ntb->spad_count; i++)
649 amd_ntb_spad_write(ntb->device, i, 0);
655 struct amd_ntb_softc *ntb = device_get_softc(dev);
660 if (idx < 0 || idx >= ntb->spad_count)
663 offset = ntb->peer_spad + (idx << 2);
673 struct amd_ntb_softc *ntb = device_get_softc(dev);
678 if (idx < 0 || idx >= ntb->spad_count)
681 offset = ntb->peer_spad + (idx << 2);
694 struct amd_ntb_softc* ntb = arg1;
704 (ntb->conn_type == NTB_CONN_PRI)? "PRIMARY" : "SECONDARY");
705 sbuf_printf(sb, "AMD LNK STA: 0x%#06x\n", ntb->lnk_sta);
707 if (!amd_link_is_up(ntb))
712 NTB_LNK_STA_SPEED(ntb->lnk_sta));
714 NTB_LNK_STA_WIDTH(ntb->lnk_sta));
718 ntb->hw_info->mw_count);
720 ntb->spad_count);
722 ntb->hw_info->db_count);
724 ntb->msix_vec_count);
726 ntb->db_valid_mask);
751 amd_ntb_sysctl_init(struct amd_ntb_softc *ntb)
756 ctx = device_get_sysctl_ctx(ntb->device);
757 globals = SYSCTL_CHILDREN(device_get_sysctl_tree(ntb->device));
760 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, ntb, 0,
768 amd_ntb_poll_link(struct amd_ntb_softc *ntb)
775 if (reg == ntb->cntl_sta)
779 __func__, fullreg, ntb->cntl_sta);
781 ntb->cntl_sta = reg;
783 stat = pci_read_config(ntb->device, AMD_LINK_STATUS_OFFSET, 4);
786 __func__, stat, ntb->lnk_sta);
788 ntb->lnk_sta = stat;
796 struct amd_ntb_softc *ntb = arg;
798 if (amd_ntb_poll_link(ntb))
799 ntb_link_event(ntb->device);
801 if (!amd_link_is_up(ntb)) {
802 callout_reset(&ntb->hb_timer, AMD_LINK_HB_TIMEOUT,
803 amd_link_hb, ntb);
805 callout_reset(&ntb->hb_timer, (AMD_LINK_HB_TIMEOUT * 10),
806 amd_link_hb, ntb);
811 amd_ntb_interrupt(struct amd_ntb_softc *ntb, uint16_t vec)
813 if (vec < ntb->hw_info->db_count)
814 ntb_db_event(ntb->device, vec);
824 amd_ntb_interrupt(nvec->ntb, nvec->num);
835 amd_init_side_info(struct amd_ntb_softc *ntb)
848 amd_deinit_side_info(struct amd_ntb_softc *ntb)
861 amd_ntb_setup_isr(struct amd_ntb_softc *ntb, uint16_t num_vectors, bool msi,
874 ntb->int_info[i].rid = i;
876 ntb->int_info[i].rid = i + 1;
878 ntb->int_info[i].res = bus_alloc_resource_any(ntb->device,
879 SYS_RES_IRQ, &ntb->int_info[i].rid, flags);
880 if (ntb->int_info[i].res == NULL) {
885 ntb->int_info[i].tag = NULL;
886 ntb->allocated_interrupts++;
889 rc = bus_setup_intr(ntb->device, ntb->int_info[i].res,
891 ntb, &ntb->int_info[i].tag);
893 rc = bus_setup_intr(ntb->device, ntb->int_info[i].res,
895 &ntb->msix_vec[i], &ntb->int_info[i].tag);
908 amd_ntb_create_msix_vec(struct amd_ntb_softc *ntb, uint32_t max_vectors)
912 ntb->msix_vec = malloc(max_vectors * sizeof(*ntb->msix_vec), M_AMD_NTB,
916 ntb->msix_vec[i].num = i;
917 ntb->msix_vec[i].ntb = ntb;
924 amd_ntb_free_msix_vec(struct amd_ntb_softc *ntb)
926 if (ntb->msix_vec_count) {
927 pci_release_msi(ntb->device);
928 ntb->msix_vec_count = 0;
931 if (ntb->msix_vec != NULL) {
932 free(ntb->msix_vec, M_AMD_NTB);
933 ntb->msix_vec = NULL;
938 amd_ntb_init_isr(struct amd_ntb_softc *ntb)
944 ntb->db_mask = ntb->db_valid_mask;
946 rc = amd_ntb_create_msix_vec(ntb, ntb->hw_info->msix_vector_count);
956 supported_vectors = pci_msix_count(ntb->device);
957 num_vectors = MIN(supported_vectors, ntb->hw_info->db_count);
958 if (num_vectors < ntb->hw_info->db_count) {
960 supported_vectors, ntb->hw_info->db_count);
966 rc = pci_alloc_msix(ntb->device, &num_vectors);
973 if (num_vectors < ntb->hw_info->db_count) {
977 * Else set ntb->hw_info->db_count = ntb->msix_vec_count =
985 free(ntb->msix_vec, M_AMD_NTB);
986 ntb->msix_vec = NULL;
987 pci_release_msi(ntb->device);
989 rc = pci_alloc_msi(ntb->device, &num_vectors);
997 ntb->hw_info->db_count = ntb->msix_vec_count = num_vectors;
1001 ntb->hw_info->db_count = 1;
1002 ntb->msix_vec_count = 0;
1006 __func__, ntb->hw_info->db_count, ntb->msix_vec_count, (int)msi, (int)intx);
1008 rc = amd_ntb_setup_isr(ntb, num_vectors, msi, intx);
1011 amd_ntb_free_msix_vec(ntb);
1018 amd_ntb_deinit_isr(struct amd_ntb_softc *ntb)
1024 ntb->db_mask = ntb->db_valid_mask;
1025 amd_ntb_reg_write(4, AMD_DBMASK_OFFSET, ntb->db_mask);
1027 for (i = 0; i < ntb->allocated_interrupts; i++) {
1028 current_int = &ntb->int_info[i];
1030 bus_teardown_intr(ntb->device, current_int->res,
1034 bus_release_resource(ntb->device, SYS_RES_IRQ,
1038 amd_ntb_free_msix_vec(ntb);
1042 amd_ntb_get_topo(struct amd_ntb_softc *ntb)
1055 amd_ntb_init_dev(struct amd_ntb_softc *ntb)
1057 ntb->db_valid_mask = (1ull << ntb->hw_info->db_count) - 1;
1058 mtx_init(&ntb->db_mask_lock, "amd ntb db bits", NULL, MTX_SPIN);
1060 switch (ntb->conn_type) {
1063 ntb->spad_count >>= 1;
1065 if (ntb->conn_type == NTB_CONN_PRI) {
1066 ntb->self_spad = 0;
1067 ntb->peer_spad = 0x20;
1069 ntb->self_spad = 0x20;
1070 ntb->peer_spad = 0;
1073 callout_init(&ntb->hb_timer, 1);
1074 callout_reset(&ntb->hb_timer, AMD_LINK_HB_TIMEOUT,
1075 amd_link_hb, ntb);
1081 ntb->conn_type);
1085 ntb->int_mask = AMD_EVENT_INTMASK;
1086 amd_ntb_reg_write(4, AMD_INTMASK_OFFSET, ntb->int_mask);
1092 amd_ntb_init(struct amd_ntb_softc *ntb)
1096 ntb->conn_type = amd_ntb_get_topo(ntb);
1098 (ntb->conn_type == NTB_CONN_PRI)? "PRIMARY" : "SECONDARY");
1100 rc = amd_ntb_init_dev(ntb);
1104 rc = amd_ntb_init_isr(ntb);
1112 print_map_success(struct amd_ntb_softc *ntb, struct amd_ntb_pci_bar_info *bar,
1133 map_bar(struct amd_ntb_softc *ntb, struct amd_ntb_pci_bar_info *bar)
1135 bar->pci_resource = bus_alloc_resource_any(ntb->device, SYS_RES_MEMORY,
1141 print_map_success(ntb, bar, "mmr");
1147 amd_ntb_map_pci_bars(struct amd_ntb_softc *ntb)
1152 ntb->bar_info[NTB_CONFIG_BAR].pci_resource_id = PCIR_BAR(0);
1153 rc = map_bar(ntb, &ntb->bar_info[NTB_CONFIG_BAR]);
1158 ntb->bar_info[NTB_BAR_1].pci_resource_id = PCIR_BAR(1);
1159 rc = map_bar(ntb, &ntb->bar_info[NTB_BAR_1]);
1162 ntb->bar_info[NTB_BAR_1].xlat_off = AMD_BAR1XLAT_OFFSET;
1163 ntb->bar_info[NTB_BAR_1].limit_off = AMD_BAR1LMT_OFFSET;
1166 ntb->bar_info[NTB_BAR_2].pci_resource_id = PCIR_BAR(2);
1167 rc = map_bar(ntb, &ntb->bar_info[NTB_BAR_2]);
1170 ntb->bar_info[NTB_BAR_2].xlat_off = AMD_BAR23XLAT_OFFSET;
1171 ntb->bar_info[NTB_BAR_2].limit_off = AMD_BAR23LMT_OFFSET;
1174 ntb->bar_info[NTB_BAR_3].pci_resource_id = PCIR_BAR(4);
1175 rc = map_bar(ntb, &ntb->bar_info[NTB_BAR_3]);
1178 ntb->bar_info[NTB_BAR_3].xlat_off = AMD_BAR45XLAT_OFFSET;
1179 ntb->bar_info[NTB_BAR_3].limit_off = AMD_BAR45LMT_OFFSET;
1189 amd_ntb_unmap_pci_bars(struct amd_ntb_softc *ntb)
1195 bar_info = &ntb->bar_info[i];
1197 bus_release_resource(ntb->device, SYS_RES_MEMORY,
1205 struct amd_ntb_softc *ntb = device_get_softc(device);
1212 ntb->hw_info = (struct amd_ntb_hw_info *)tbl->driver_data;
1213 ntb->spad_count = ntb->hw_info->spad_count;
1222 struct amd_ntb_softc *ntb = device_get_softc(device);
1225 ntb->device = device;
1228 pci_enable_busmaster(ntb->device);
1230 error = amd_ntb_map_pci_bars(ntb);
1234 error = amd_ntb_init(ntb);
1238 amd_init_side_info(ntb);
1240 amd_ntb_spad_clear(ntb);
1242 amd_ntb_sysctl_init(ntb);
1257 struct amd_ntb_softc *ntb = device_get_softc(device);
1260 amd_deinit_side_info(ntb);
1261 callout_drain(&ntb->hb_timer);
1262 amd_ntb_deinit_isr(ntb);
1263 mtx_destroy(&ntb->db_mask_lock);
1264 pci_disable_busmaster(ntb->device);
1265 amd_ntb_unmap_pci_bars(ntb);
1314 MODULE_DEPEND(ntb_hw_amd, ntb, 1, 1, 1);