Lines Matching refs:NFE_WRITE
457 NFE_WRITE(sc, NFE_MSIX_MAP0, 0);
458 NFE_WRITE(sc, NFE_MSIX_MAP1, 0);
460 NFE_WRITE(sc, NFE_MSI_MAP0, 0);
461 NFE_WRITE(sc, NFE_MSI_MAP1, 0);
868 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2);
869 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC);
871 NFE_WRITE(sc, NFE_MAC_RESET, 0);
873 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2);
880 NFE_WRITE(sc, NFE_PWR2_CTL, pwr);
920 NFE_WRITE(sc, NFE_TX_CTL, txctl);
921 NFE_WRITE(sc, NFE_RX_CTL, rxctl);
970 NFE_WRITE(sc, NFE_SETUP_R1, val);
972 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */
974 NFE_WRITE(sc, NFE_PHY_IFACE, phy);
975 NFE_WRITE(sc, NFE_MISC1, misc);
976 NFE_WRITE(sc, NFE_LINKSPEED, link);
986 NFE_WRITE(sc, NFE_RXFILTER, val);
991 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME,
996 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME,
999 NFE_WRITE(sc, NFE_MISC1, val);
1005 NFE_WRITE(sc, NFE_RXFILTER, val);
1007 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME,
1011 NFE_WRITE(sc, NFE_MISC1, val);
1023 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
1026 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
1030 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg);
1063 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
1066 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
1070 NFE_WRITE(sc, NFE_PHY_DATA, val);
1072 NFE_WRITE(sc, NFE_PHY_CTL, ctl);
1644 NFE_WRITE(sc, sc->nfe_irq_status, r);
1648 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
1662 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED);
1673 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_intrs);
1675 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_intrs);
1685 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_nointrs);
1687 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_nointrs);
1873 NFE_WRITE(sc, sc->nfe_irq_status, r);
1886 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
2579 NFE_WRITE(sc, NFE_MULTIADDR_HI, ctx.addr[3] << 24 | ctx.addr[2] << 16 |
2581 NFE_WRITE(sc, NFE_MULTIADDR_LO,
2583 NFE_WRITE(sc, NFE_MULTIMASK_HI, ctx.mask[3] << 24 | ctx.mask[2] << 16 |
2585 NFE_WRITE(sc, NFE_MULTIMASK_LO,
2592 NFE_WRITE(sc, NFE_RXFILTER, filter);
2640 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl);
2673 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl);
2730 NFE_WRITE(sc, NFE_TX_UNK, val);
2731 NFE_WRITE(sc, NFE_STATUS, 0);
2734 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, NFE_TX_PAUSE_FRAME_DISABLE);
2747 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl);
2749 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
2752 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE);
2754 NFE_WRITE(sc, NFE_VTAG_CTL, 0);
2756 NFE_WRITE(sc, NFE_SETUP_R6, 0);
2763 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI,
2765 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO,
2768 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI,
2770 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO,
2773 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, NFE_ADDR_HI(sc->txq.physaddr));
2774 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, NFE_ADDR_LO(sc->txq.physaddr));
2776 NFE_WRITE(sc, NFE_RING_SIZE,
2780 NFE_WRITE(sc, NFE_RXBUFSZ, sc->nfe_framesize);
2785 NFE_WRITE(sc, NFE_PWR_STATE, val | NFE_PWR_WAKEUP);
2788 NFE_WRITE(sc, NFE_PWR_STATE, val | NFE_PWR_VALID);
2792 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT);
2795 NFE_WRITE(sc, NFE_IMTIMER, 970);
2798 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC_10_100);
2799 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC);
2800 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC);
2803 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC);
2805 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC);
2807 NFE_WRITE(sc, NFE_WOL_CTL, 0);
2810 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
2812 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl);
2818 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START);
2821 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START);
2823 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
2864 NFE_WRITE(sc, NFE_TX_CTL, 0);
2867 NFE_WRITE(sc, NFE_RX_CTL, 0);
3009 NFE_WRITE(sc, NFE_MACADDR_LO, addr[5] << 8 | addr[4]);
3010 NFE_WRITE(sc, NFE_MACADDR_HI, addr[3] << 24 | addr[2] << 16 |
3339 NFE_WRITE(sc, NFE_WOL_CTL, wolctl);
3343 NFE_WRITE(sc, NFE_PWR2_CTL,
3346 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, 0);
3347 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, 0);
3348 NFE_WRITE(sc, NFE_RX_CTL, NFE_READ(sc, NFE_RX_CTL) |