Lines Matching refs:mh
100 pCmd = (type *)&mh->mh_cmdbuf[0]; \
129 struct mwl_hal_priv *mh; /* back pointer */
138 #define MWLVAP(_vap) ((_vap)->mh)
199 MWL_HAL_LOCK(struct mwl_hal_priv *mh)
201 mtx_lock(&mh->mh_mtx);
205 MWL_HAL_LOCK_ASSERT(struct mwl_hal_priv *mh)
207 mtx_assert(&mh->mh_mtx, MA_OWNED);
211 MWL_HAL_UNLOCK(struct mwl_hal_priv *mh)
213 mtx_unlock(&mh->mh_mtx);
217 RD4(struct mwl_hal_priv *mh, bus_size_t off)
219 return bus_space_read_4(mh->public.mh_iot, mh->public.mh_ioh, off);
223 WR4(struct mwl_hal_priv *mh, bus_size_t off, uint32_t val)
225 bus_space_write_4(mh->public.mh_iot, mh->public.mh_ioh, off, val);
248 struct mwl_hal_priv *mh;
252 mh = malloc(sizeof(struct mwl_hal_priv), M_DEVBUF, M_NOWAIT | M_ZERO);
253 if (mh == NULL)
255 mh->mh_dev = dev;
256 mh->public.mh_ioh = ioh;
257 mh->public.mh_iot = iot;
259 mh->mh_streams[i].public.txq = ba2qid[i];
260 mh->mh_streams[i].stream = i;
262 if (mh->mh_streams[i].public.txq < MWL_BAQID_MAX)
263 qid2ba[mh->mh_streams[i].public.txq] = i;
266 "stream %d\n", mh->mh_streams[i].public.txq, i);
271 hvap = &mh->mh_vaps[i];
276 hvap = &mh->mh_vaps[i];
281 hvap = &mh->mh_vaps[i];
286 hvap = &mh->mh_vaps[i];
291 mh->mh_revs.mh_devid = devid;
292 snprintf(mh->mh_mtxname, sizeof(mh->mh_mtxname),
294 mtx_init(&mh->mh_mtx, mh->mh_mtxname, NULL, MTX_DEF);
312 &mh->mh_dmat);
320 error = bus_dmamem_alloc(mh->mh_dmat, (void**) &mh->mh_cmdbuf,
322 &mh->mh_dmamap);
329 error = bus_dmamap_load(mh->mh_dmat, mh->mh_dmamap,
330 mh->mh_cmdbuf, MWL_CMDBUF_SIZE,
331 mwl_hal_load_cb, &mh->mh_cmdaddr,
351 mh->mh_SDRAMSIZE_Addr = 0x40fe70b7; /* 8M SDRAM */
354 mh->mh_SDRAMSIZE_Addr = 0x40fc70b7; /* 16M SDRAM */
359 return &mh->public;
361 bus_dmamem_free(mh->mh_dmat, mh->mh_cmdbuf, mh->mh_dmamap);
363 bus_dma_tag_destroy(mh->mh_dmat);
365 mtx_destroy(&mh->mh_mtx);
366 free(mh, M_DEVBUF);
373 struct mwl_hal_priv *mh = MWLPRIV(mh0);
375 bus_dmamem_free(mh->mh_dmat, mh->mh_cmdbuf, mh->mh_dmamap);
376 bus_dma_tag_destroy(mh->mh_dmat);
377 mtx_destroy(&mh->mh_mtx);
378 free(mh, M_DEVBUF);
385 mwlResetHalState(struct mwl_hal_priv *mh)
390 mh->mh_bastreams = (1<<MWL_BASTREAMS_MAX)-1;
392 mh->mh_vaps[i].mh = NULL;
396 mh->mh_RTSSuccesses = 0;
397 mh->mh_RTSFailures = 0;
398 mh->mh_RxDuplicateFrames = 0;
399 mh->mh_FCSErrorCount = 0;
405 if ((mh->mh_flags & MHF_CALDATA) == 0)
406 mwlGetPwrCalTable(mh);
414 struct mwl_hal_priv *mh = MWLPRIV(mh0);
418 MWL_HAL_LOCK(mh);
421 vap = &mh->mh_vaps[i];
422 if (vap->vap_type == type && vap->mh == NULL) {
423 vap->mh = mh;
428 MWL_HAL_UNLOCK(mh);
436 vap->mh = NULL;
446 mwl_hal_setdebug(struct mwl_hal *mh, int debug)
448 MWLPRIV(mh)->mh_debug = debug;
452 mwl_hal_getdebug(struct mwl_hal *mh)
454 return MWLPRIV(mh)->mh_debug;
458 mwl_hal_setbastreams(struct mwl_hal *mh, int mask)
460 MWLPRIV(mh)->mh_bastreams = mask & ((1<<MWL_BASTREAMS_MAX)-1);
464 mwl_hal_getbastreams(struct mwl_hal *mh)
466 return MWLPRIV(mh)->mh_bastreams;
470 mwl_hal_ismbsscapable(struct mwl_hal *mh)
472 return (MWLPRIV(mh)->mh_flags & MHF_MBSS) != 0;
484 struct mwl_hal_priv *mh = MWLPRIV(mh0);
487 cause = RD4(mh, MACREG_REG_A2H_INTERRUPT_CAUSE);
489 device_printf(mh->mh_dev, "%s: cause 0x%x\n", __func__, cause);
493 WR4(mh, MACREG_REG_A2H_INTERRUPT_CAUSE,
494 cause &~ mh->public.mh_imask);
495 RD4(mh, MACREG_REG_INT_CODE); /* XXX flush write? */
507 struct mwl_hal_priv *mh = MWLPRIV(mh0);
509 WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, 0);
510 RD4(mh, MACREG_REG_INT_CODE);
512 mh->public.mh_imask = mask;
513 WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, mask);
514 RD4(mh, MACREG_REG_INT_CODE);
527 struct mwl_hal_priv *mh = MWLPRIV(mh0);
530 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_PPA_READY);
531 dummy = RD4(mh, MACREG_REG_INT_CODE);
544 struct mwl_hal_priv *mh = MWLPRIV(mh0);
546 if (mh->mh_debug & MWL_HAL_DEBUG_CMDDONE) {
547 device_printf(mh->mh_dev, "cmd done interrupt:\n");
548 dumpresult(mh, 1);
562 struct mwl_hal_priv *mh = MWLPRIV(mh0);
566 MWL_HAL_LOCK(mh);
569 pCmd->ulFwAwakeCookie = htole32((unsigned int)mh->mh_cmdaddr+2048);
571 retval = mwlExecuteCmd(mh, HostCmd_CMD_GET_HW_SPEC);
588 mh->mh_revs.mh_macRev = hw->hwVersion; /* XXX */
589 mh->mh_revs.mh_phyRev = hw->hostInterface; /* XXX */
594 mh->mh_bastreams &= (1<<MWL_BASTREAMS_MAX)-1;
596 mh->mh_bastreams &= (1<<2)-1;
598 MWL_HAL_UNLOCK(mh);
610 struct mwl_hal_priv *mh = MWLPRIV(mh0);
614 MWL_HAL_LOCK(mh);
630 if (mh->mh_revs.mh_macRev < 5)
633 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_HW_SPEC);
636 mh->mh_flags &= ~MHF_MBSS;
638 mh->mh_flags |= MHF_MBSS;
640 MWL_HAL_UNLOCK(mh);
651 struct mwl_hal_priv *mh = MWLPRIV(mh0);
655 MWL_HAL_LOCK(mh);
659 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_GET_STAT);
673 mh->mh_RTSSuccesses += RD4(mh, 0xa834);
674 mh->mh_RTSFailures += RD4(mh, 0xa830);
675 mh->mh_RxDuplicateFrames += RD4(mh, 0xa84c);
676 mh->mh_FCSErrorCount += RD4(mh, 0xa840);
678 MWL_HAL_UNLOCK(mh);
680 stats->RTSSuccesses = mh->mh_RTSSuccesses;
681 stats->RTSFailures = mh->mh_RTSFailures;
682 stats->RxDuplicateFrames = mh->mh_RxDuplicateFrames;
683 stats->FCSErrorCount = mh->mh_FCSErrorCount;
694 struct mwl_hal_priv *mh = MWLVAP(vap);
698 MWL_HAL_LOCK(mh);
711 retval = mwlExecuteCmd(mh, HostCmd_CMD_HT_GUARD_INTERVAL);
712 MWL_HAL_UNLOCK(mh);
724 struct mwl_hal_priv *mh = MWLPRIV(mh0);
728 MWL_HAL_LOCK(mh);
738 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_RADIO_CONTROL);
739 MWL_HAL_UNLOCK(mh);
752 struct mwl_hal_priv *mh = MWLPRIV(mh0);
759 MWL_HAL_LOCK(mh);
767 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_RF_ANTENNA);
768 MWL_HAL_UNLOCK(mh);
780 struct mwl_hal_priv *mh = MWLVAP(vap);
784 MWL_HAL_LOCK(mh);
790 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_RTS_THSD);
791 MWL_HAL_UNLOCK(mh);
801 struct mwl_hal_priv *mh = MWLVAP(vap);
805 MWL_HAL_LOCK(mh);
809 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_INFRA_MODE);
810 MWL_HAL_UNLOCK(mh);
820 struct mwl_hal_priv *mh = MWLPRIV(mh0);
824 MWL_HAL_LOCK(mh);
829 if (mh->mh_regioncode == DOMAIN_CODE_ETSI_131)
832 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11H_DETECT_RADAR);
833 MWL_HAL_UNLOCK(mh);
889 struct mwl_hal_priv *mh = MWLPRIV(mh0);
893 MWL_HAL_LOCK(mh);
901 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_SWITCH_CHANNEL);
902 MWL_HAL_UNLOCK(mh);
912 struct mwl_hal_priv *mh = MWLPRIV(mh0);
916 MWL_HAL_LOCK(mh);
929 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_REGION_CODE);
931 mh->mh_regioncode = regionCode;
932 MWL_HAL_UNLOCK(mh);
943 struct mwl_hal_priv *mh = MWLVAP(vap);
948 MWL_HAL_LOCK(mh);
988 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_FIXED_RATE);
989 MWL_HAL_UNLOCK(mh);
996 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1000 MWL_HAL_LOCK(mh);
1011 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_FIXED_RATE);
1012 MWL_HAL_UNLOCK(mh);
1022 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1029 MWL_HAL_LOCK(mh);
1035 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_SET_SLOT);
1036 MWL_HAL_UNLOCK(mh);
1043 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1047 MWL_HAL_LOCK(mh);
1060 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_RF_TX_POWER);
1061 MWL_HAL_UNLOCK(mh);
1066 findchannel(const struct mwl_hal_priv *mh, const MWL_HAL_CHANNEL *c)
1075 ci = &mh->mh_40M;
1079 ci = &mh->mh_20M;
1084 ci = &mh->mh_40M_5G;
1088 ci = &mh->mh_20M_5G;
1102 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1107 hc = findchannel(mh, c);
1110 device_printf(mh->mh_dev,
1117 MWL_HAL_LOCK(mh);
1131 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_RF_TX_POWER);
1132 MWL_HAL_UNLOCK(mh);
1140 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1144 *ci = (chw == MWL_CH_20_MHz_WIDTH) ? &mh->mh_20M : &mh->mh_40M;
1148 &mh->mh_20M_5G : &mh->mh_40M_5G;
1159 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1166 MWL_HAL_LOCK(mh);
1173 retval = mwlExecuteCmd(mh, HostCmd_CMD_MAC_MULTICAST_ADR);
1174 MWL_HAL_UNLOCK(mh);
1182 struct mwl_hal_priv *mh = MWLVAP(vap);
1186 MWL_HAL_LOCK(mh);
1223 retval = mwlExecuteCmd(mh, HostCmd_CMD_UPDATE_ENCRYPTION);
1224 MWL_HAL_UNLOCK(mh);
1231 struct mwl_hal_priv *mh = MWLVAP(vap);
1235 MWL_HAL_LOCK(mh);
1248 retval = mwlExecuteCmd(mh, HostCmd_CMD_UPDATE_ENCRYPTION);
1249 MWL_HAL_UNLOCK(mh);
1257 struct mwl_hal_priv *mh = MWLVAP(vap);
1266 return mwlExecuteCmd(mh, HostCmd_CMD_SET_MAC_ADDR);
1272 struct mwl_hal_priv *mh = MWLVAP(vap);
1275 MWL_HAL_LOCK(mh);
1277 MWL_HAL_UNLOCK(mh);
1284 struct mwl_hal_priv *mh = MWLVAP(vap);
1289 MWL_HAL_LOCK(mh);
1296 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_BEACON);
1297 MWL_HAL_UNLOCK(mh);
1304 struct mwl_hal_priv *mh = MWLVAP(vap);
1308 MWL_HAL_LOCK(mh);
1313 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_POWERSAVESTATION);
1314 MWL_HAL_UNLOCK(mh);
1321 struct mwl_hal_priv *mh = MWLVAP(vap);
1325 MWL_HAL_LOCK(mh);
1330 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_TIM);
1331 MWL_HAL_UNLOCK(mh);
1339 struct mwl_hal_priv *mh = MWLVAP(vap);
1340 HostCmd_FW_SET_AID *pCmd = (HostCmd_FW_SET_AID *) &mh->mh_cmdbuf[0];
1343 MWL_HAL_LOCK(mh);
1348 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_AID);
1349 MWL_HAL_UNLOCK(mh);
1356 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1360 MWL_HAL_LOCK(mh);
1366 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_RF_CHANNEL);
1367 MWL_HAL_UNLOCK(mh);
1376 struct mwl_hal_priv *mh = MWLVAP(vap);
1380 MWL_HAL_LOCK_ASSERT(mh);
1401 retval = mwlExecuteCmd(mh, HostCmd_CMD_BASTREAM);
1419 struct mwl_hal_priv *mh = MWLVAP(vap);
1423 MWL_HAL_LOCK(mh);
1424 if (mh->mh_bastreams == 0) {
1426 MWL_HAL_UNLOCK(mh);
1429 for (s = 0; (mh->mh_bastreams & (1<<s)) == 0; s++)
1432 MWL_HAL_UNLOCK(mh);
1435 sp = &mh->mh_streams[s];
1436 mh->mh_bastreams &= ~(1<<s);
1444 MWL_HAL_UNLOCK(mh);
1451 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1455 if (mh->mh_bastreams & (1<<s))
1457 return &mh->mh_streams[s].public;
1468 struct mwl_hal_priv *mh = MWLVAP(vap);
1473 MWL_HAL_LOCK(mh);
1502 retval = mwlExecuteCmd(mh, HostCmd_CMD_BASTREAM);
1514 MWL_HAL_UNLOCK(mh);
1521 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1530 MWL_HAL_LOCK(mh);
1537 retval = mwlExecuteCmd(mh, HostCmd_CMD_BASTREAM);
1541 mh->mh_bastreams |= 1<<sp->stream;
1545 MWL_HAL_UNLOCK(mh);
1554 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1559 MWL_HAL_LOCK(mh);
1564 retval = mwlExecuteCmd(mh, HostCmd_CMD_GET_SEQNO);
1567 MWL_HAL_UNLOCK(mh);
1574 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1578 MWL_HAL_LOCK(mh);
1582 retval = mwlExecuteCmd(mh, HostCmd_CMD_GET_WATCHDOG_BITMAP);
1589 MWL_HAL_UNLOCK(mh);
1599 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1603 MWL_HAL_LOCK(mh);
1610 retval = mwlExecuteCmd(mh, HostCmd_CMD_AMPDU_RETRY_RATEDROP_MODE);
1611 MWL_HAL_UNLOCK(mh);
1618 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1622 MWL_HAL_LOCK(mh);
1627 retval = mwlExecuteCmd(mh, HostCmd_CMD_AMPDU_RETRY_RATEDROP_MODE);
1628 MWL_HAL_UNLOCK(mh);
1640 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1644 MWL_HAL_LOCK(mh);
1649 retval = mwlExecuteCmd(mh, HostCmd_CMD_CFEND_ENABLE);
1650 MWL_HAL_UNLOCK(mh);
1658 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1661 MWL_HAL_LOCK(mh);
1664 retval = mwlExecuteCmd(mh, HostCmd_CMD_DWDS_ENABLE);
1665 MWL_HAL_UNLOCK(mh);
1689 struct mwl_hal_priv *mh = MWLVAP(vap);
1693 MWL_HAL_LOCK(mh);
1706 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_NEW_STN);
1709 MWL_HAL_UNLOCK(mh);
1717 struct mwl_hal_priv *mh = MWLVAP(vap);
1721 MWL_HAL_LOCK(mh);
1728 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_NEW_STN);
1733 MWL_HAL_UNLOCK(mh);
1744 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1748 MWL_HAL_LOCK(mh);
1757 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_KEEP_ALIVE);
1758 MWL_HAL_UNLOCK(mh);
1765 struct mwl_hal_priv *mh = MWLVAP(vap);
1771 MWL_HAL_LOCK(mh);
1775 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_APMODE);
1776 MWL_HAL_UNLOCK(mh);
1783 struct mwl_hal_priv *mh = MWLVAP(vap);
1787 MWL_HAL_LOCK(mh);
1792 retval = mwlExecuteCmd(mh, HostCmd_CMD_BSS_START);
1797 MWL_HAL_UNLOCK(mh);
1804 struct mwl_hal_priv *mh = MWLVAP(vap);
1808 MWL_HAL_LOCK(mh);
1812 retval = mwlExecuteCmd(mh, HostCmd_CMD_BSS_START);
1815 MWL_HAL_UNLOCK(mh);
1822 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1826 MWL_HAL_LOCK(mh);
1831 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_G_PROTECT_FLAG);
1832 MWL_HAL_UNLOCK(mh);
1839 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1843 MWL_HAL_LOCK(mh);
1848 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_WMM_MODE);
1849 MWL_HAL_UNLOCK(mh);
1857 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1861 MWL_HAL_LOCK(mh);
1876 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_EDCA_PARAMS);
1877 MWL_HAL_UNLOCK(mh);
1885 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1889 MWL_HAL_LOCK(mh);
1895 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_RATE_ADAPT_MODE);
1896 MWL_HAL_UNLOCK(mh);
1903 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1907 MWL_HAL_LOCK(mh);
1913 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_LINKADAPT_CS_MODE);
1914 MWL_HAL_UNLOCK(mh);
1921 struct mwl_hal_priv *mh = MWLVAP(vap);
1926 MWL_HAL_LOCK(mh);
1931 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_N_PROTECT_FLAG);
1932 MWL_HAL_UNLOCK(mh);
1939 struct mwl_hal_priv *mh = MWLVAP(vap);
1943 MWL_HAL_LOCK(mh);
1948 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_N_PROTECT_OPMODE);
1949 MWL_HAL_UNLOCK(mh);
1956 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1960 MWL_HAL_LOCK(mh);
1965 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_OPTIMIZATION_LEVEL);
1966 MWL_HAL_UNLOCK(mh);
1974 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1978 MWL_HAL_LOCK(mh);
1984 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_MIMOPSHT);
1985 MWL_HAL_UNLOCK(mh);
1990 mwlGetCalTable(struct mwl_hal_priv *mh, uint8_t annex, uint8_t index)
1995 MWL_HAL_LOCK_ASSERT(mh);
2002 retval = mwlExecuteCmd(mh, HostCmd_CMD_GET_CALTABLE);
2099 mwlGetPwrCalTable(struct mwl_hal_priv *mh)
2105 MWL_HAL_LOCK(mh);
2107 data = ((const HostCmd_FW_GET_CALTABLE *) mh->mh_cmdbuf)->calTbl;
2108 if (mwlGetCalTable(mh, 33, 0) == 0) {
2115 get2Ghz(&mh->mh_20M, &data[12], len);
2117 if (mwlGetCalTable(mh, 34, 0) == 0) {
2124 ci = &mh->mh_40M;
2127 if (mwlGetCalTable(mh, 35, 0) == 0) {
2134 get5Ghz(&mh->mh_20M_5G, &data[20], len);
2136 if (mwlGetCalTable(mh, 36, 0) == 0) {
2143 ci = &mh->mh_40M_5G;
2146 mh->mh_flags |= MHF_CALDATA;
2147 MWL_HAL_UNLOCK(mh);
2154 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2157 MWL_HAL_LOCK(mh);
2158 retval = mwlGetCalTable(mh, 0, 0);
2161 (const HostCmd_FW_GET_CALTABLE *) mh->mh_cmdbuf;
2164 MWL_HAL_UNLOCK(mh);
2171 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2174 MWL_HAL_LOCK(mh);
2175 v = RD4(mh, MACREG_REG_PROMISCUOUS);
2176 WR4(mh, MACREG_REG_PROMISCUOUS, ena ? v | 1 : v &~ 1);
2177 MWL_HAL_UNLOCK(mh);
2184 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2187 MWL_HAL_LOCK(mh);
2188 v = RD4(mh, MACREG_REG_PROMISCUOUS);
2189 MWL_HAL_UNLOCK(mh);
2196 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2200 MWL_HAL_LOCK(mh);
2204 retval = mwlExecuteCmd(mh, HostCmd_CMD_GET_BEACON);
2210 MWL_HAL_UNLOCK(mh);
2217 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2221 MWL_HAL_LOCK(mh);
2225 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_RIFS);
2226 MWL_HAL_UNLOCK(mh);
2235 getRFReg(struct mwl_hal_priv *mh, int flag, uint32_t reg, uint32_t *val)
2240 MWL_HAL_LOCK(mh);
2246 retval = mwlExecuteCmd(mh, HostCmd_CMD_RF_REG_ACCESS);
2249 MWL_HAL_UNLOCK(mh);
2254 getBBReg(struct mwl_hal_priv *mh, int flag, uint32_t reg, uint32_t *val)
2259 MWL_HAL_LOCK(mh);
2265 retval = mwlExecuteCmd(mh, HostCmd_CMD_BBP_REG_ACCESS);
2268 MWL_HAL_UNLOCK(mh);
2273 mwl_hal_getregdump(struct mwl_hal_priv *mh, const MWL_DIAG_REGRANGE *regs,
2286 *dp = RD4(mh, r);
2288 getBBReg(mh, HostCmd_ACT_GEN_READ,
2291 getRFReg(mh, HostCmd_ACT_GEN_READ,
2294 *dp = RD4(mh, r);
2310 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2314 *result = &mh->mh_revs;
2315 *resultsize = sizeof(mh->mh_revs);
2318 *resultsize = mwl_hal_getregdump(mh, args, *result, *resultsize);
2321 FWCmdHdr *pCmd = (FWCmdHdr *) &mh->mh_cmdbuf[0];
2324 MWL_HAL_LOCK(mh);
2326 retval = mwlExecuteCmd(mh, le16toh(pCmd->Cmd));
2328 MWL_HAL_UNLOCK(mh);
2333 device_printf(mh->mh_dev, "problem loading fw image\n");
2346 mwlSendCmd(struct mwl_hal_priv *mh)
2350 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap,
2353 WR4(mh, MACREG_REG_GEN_PTR, mh->mh_cmdaddr);
2354 dummy = RD4(mh, MACREG_REG_INT_CODE);
2356 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_DOOR_BELL);
2360 mwlWaitForCmdComplete(struct mwl_hal_priv *mh, uint16_t cmdCode)
2366 if (mh->mh_cmdbuf[0] == le16toh(cmdCode))
2375 mwlExecuteCmd(struct mwl_hal_priv *mh, unsigned short cmd)
2378 MWL_HAL_LOCK_ASSERT(mh);
2380 if ((mh->mh_flags & MHF_FWHANG) &&
2381 (mh->mh_debug & MWL_HAL_DEBUG_IGNHANG) == 0) {
2383 device_printf(mh->mh_dev, "firmware hung, skipping cmd %s\n",
2386 device_printf(mh->mh_dev, "firmware hung, skipping cmd 0x%x\n",
2391 if (RD4(mh, MACREG_REG_INT_CODE) == 0xffffffff) {
2392 device_printf(mh->mh_dev, "%s: device not present!\n",
2397 if (mh->mh_debug & MWL_HAL_DEBUG_SENDCMD)
2398 dumpresult(mh, 0);
2400 mwlSendCmd(mh);
2401 if (!mwlWaitForCmdComplete(mh, 0x8000 | cmd)) {
2403 device_printf(mh->mh_dev,
2406 device_printf(mh->mh_dev,
2409 mh->mh_flags |= MHF_FWHANG;
2412 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap,
2415 if (mh->mh_debug & MWL_HAL_DEBUG_CMDDONE)
2416 dumpresult(mh, 1);
2435 mwlFwReset(struct mwl_hal_priv *mh)
2437 if (RD4(mh, MACREG_REG_INT_CODE) == 0xffffffff) {
2438 device_printf(mh->mh_dev, "%s: device not present!\n",
2442 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, ISR_RESET);
2443 mh->mh_flags &= ~MHF_FWHANG;
2447 mwlTriggerPciCmd(struct mwl_hal_priv *mh)
2451 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap, BUS_DMASYNC_PREWRITE);
2453 WR4(mh, MACREG_REG_GEN_PTR, mh->mh_cmdaddr);
2454 dummy = RD4(mh, MACREG_REG_INT_CODE);
2456 WR4(mh, MACREG_REG_INT_CODE, 0x00);
2457 dummy = RD4(mh, MACREG_REG_INT_CODE);
2459 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_DOOR_BELL);
2460 dummy = RD4(mh, MACREG_REG_INT_CODE);
2464 mwlWaitFor(struct mwl_hal_priv *mh, uint32_t val)
2470 if (RD4(mh, MACREG_REG_INT_CODE) == val)
2480 mwlSendBlock(struct mwl_hal_priv *mh, int bsize, const void *data, size_t dsize)
2482 mh->mh_cmdbuf[0] = htole16(HostCmd_CMD_CODE_DNLD);
2483 mh->mh_cmdbuf[1] = htole16(bsize);
2484 memcpy(&mh->mh_cmdbuf[4], data , dsize);
2485 mwlTriggerPciCmd(mh);
2487 if (mwlWaitFor(mh, MACREG_INT_CODE_CMD_FINISHED)) {
2488 WR4(mh, MACREG_REG_INT_CODE, 0);
2491 device_printf(mh->mh_dev,
2493 __func__, RD4(mh, MACREG_REG_INT_CODE));
2501 mwlSendBlock2(struct mwl_hal_priv *mh, const void *data, size_t dsize)
2503 memcpy(&mh->mh_cmdbuf[0], data, dsize);
2504 mwlTriggerPciCmd(mh);
2505 if (mwlWaitFor(mh, MACREG_INT_CODE_CMD_FINISHED)) {
2506 WR4(mh, MACREG_REG_INT_CODE, 0);
2509 device_printf(mh->mh_dev,
2511 __func__, RD4(mh, MACREG_REG_INT_CODE));
2516 mwlPokeSdramController(struct mwl_hal_priv *mh, int SDRAMSIZE_Addr)
2519 WR4(mh, 0x00006014, 0x33);
2520 WR4(mh, 0x00006018, 0xa3a2632);
2521 WR4(mh, 0x00006010, SDRAMSIZE_Addr);
2527 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2542 device_printf(mh->mh_dev,
2549 device_printf(mh->mh_dev, "firmware image %s too small\n",
2561 device_printf(mh->mh_dev,
2569 mwlFwReset(mh);
2571 WR4(mh, MACREG_REG_A2H_INTERRUPT_CLEAR_SEL, MACREG_A2HRIC_BIT_MASK);
2572 WR4(mh, MACREG_REG_A2H_INTERRUPT_CAUSE, 0x00);
2573 WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, 0x00);
2574 WR4(mh, MACREG_REG_A2H_INTERRUPT_STATUS_MASK, MACREG_A2HRIC_BIT_MASK);
2575 if (mh->mh_SDRAMSIZE_Addr != 0) {
2577 mwlPokeSdramController(mh, mh->mh_SDRAMSIZE_Addr);
2579 device_printf(mh->mh_dev, "load %s firmware image (%u bytes)\n",
2592 if (!mwlSendBlock(mh, fwboot->datasize, fwboot->data, fwboot->datasize) ||
2593 !mwlSendBlock(mh, 0, NULL, 0)) {
2598 if (mh->mh_SDRAMSIZE_Addr != 0) {
2600 mwlPokeSdramController(mh, mh->mh_SDRAMSIZE_Addr);
2604 WR4(mh, MACREG_REG_INT_CODE, 0);
2605 blocksize = RD4(mh, MACREG_REG_SCRATCH);
2633 if (!mwlSendBlock2(mh, fp, nbytes)) {
2643 if (!mwlSendBlock(mh, FW_DOWNLOAD_BLOCK_SIZE, fp, nbytes)) {
2659 mh->mh_cmdbuf[1] = 0;
2664 mwlTriggerPciCmd(mh);
2666 WR4(mh, MACREG_REG_GEN_PTR, OpMode);
2668 if (RD4(mh, MACREG_REG_INT_CODE) == FwReadySignature) {
2669 WR4(mh, MACREG_REG_INT_CODE, 0x00);
2670 return mwlResetHalState(mh);
2675 mwlFwReset(mh);
2746 dumpresult(struct mwl_hal_priv *mh, int showresult)
2748 const FWCmdHdr *h = (const FWCmdHdr *)mh->mh_cmdbuf;
2754 device_printf(mh->mh_dev, "Cmd %s Length %d SeqNum %d MacId %d",
2757 device_printf(mh->mh_dev, "Cmd %s Length %d SeqNum %d",