Lines Matching refs:x7
44 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x7,
564 u8 reserved4[0x7];
612 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
631 u8 mlid[0x7];
1067 u8 log_max_mrw_sz[0x7];
1217 u8 reserved_40[0x7];
1231 u8 reserved_45[0x7];
1394 u8 reserved_1[0x7];
1914 MLX5_QPC_ST_QP0 = 0x7,
1938 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1948 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1970 u8 reserved_2[0x7];
2607 u8 reserved_at_6[0x7];
2672 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST = 0x7,
3061 u8 reserved_2[0x7];
3165 u8 reserved_0[0x7];
3296 u8 status[0x7];
3323 u8 method[0x7];
7827 u8 reserved_3[0x7];
7868 u8 reserved_3[0x7];
7894 u8 reserved_6[0x7];
8229 u8 reserved_0[0x7];
8554 u8 reserved_0[0x7];
8837 u8 fullness_threshold[0x7];
8905 u8 sensor_index[0x7];
9605 u8 bw_allocation[0x7];
9718 u8 reserved_0[0x7];
9724 u8 mlid[0x7];
9760 u8 reserved_0[0x7];
9776 u8 reserved_4[0x7];
9781 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
9809 u8 status[0x7];
9861 u8 reserved_at_1[0x7];
9901 MLX5_VSC_DOMAIN_SCAN_CRSPACE = 0x7,
9952 MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7,
10515 u8 control_progress[0x7];
10684 u8 sensor_count[0x7];
10687 u8 internal_sensor_count[0x7];
10694 u8 sensor_count[0x7];
10708 u8 internal_sensor_count[0x7];