Lines Matching refs:x3
37 MLX5_EVENT_TYPE_SQ_DRAINED = 0x3,
73 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3,
83 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
477 MLX5_FLOW_CONTEXT_DEST_TYPE_QP = 0x3,
512 u8 first_prio[0x3];
545 u8 outer_second_prio[0x3];
548 u8 inner_second_prio[0x3];
598 u8 priority[0x3];
600 u8 sel[0x3];
635 u8 reserved_2[0x3];
657 u8 eth_prio[0x3];
1016 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1024 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1037 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1189 u8 reserved_33[0x3];
1223 u8 reserved_42[0x3];
1225 u8 reserved_43[0x3];
1235 u8 reserved_46[0x3];
1237 u8 reserved_47[0x3];
1239 u8 reserved_48[0x3];
1241 u8 reserved_49[0x3];
1247 u8 reserved_51[0x3];
1249 u8 reserved_52[0x3];
1251 u8 reserved_53[0x3];
1254 u8 reserved_54[0x3];
1256 u8 reserved_55[0x3];
1258 u8 reserved_56[0x3];
1260 u8 reserved_57[0x3];
1270 u8 reserved_60[0x3];
1272 u8 reserved_61[0x3];
1280 u8 reserved_at_460[0x3];
1282 u8 reserved_at_468[0x3];
1348 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1372 MLX5_WQ_TYPE_STRQ_CYCLIC = 0x3,
1393 u8 log2_hds_buf_size[0x3];
1412 u8 reserved_5[0x3];
1414 u8 reserved_6[0x3];
1418 u8 single_wqe_log_num_of_strides[0x3];
1421 u8 single_stride_log_num_of_bytes[0x3];
1449 u8 cnp_802p_prio[0x3];
1459 u8 reserved_2[0x3];
1633 u8 version_oper[0x3];
1635 u8 version_admin[0x3];
1638 u8 reserved_4[0x3];
1648 u8 reserved_8[0x3];
1669 u8 stall_cnt[0x3];
1722 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE = 0x3,
1758 u8 reserved_1[0x3];
1901 MLX5_QPC_STATE_RTS = 0x3,
1912 MLX5_QPC_ST_XRC = 0x3,
1924 MLX5_QP_PM_MIGRATED = 0x3,
1935 MLX5_QPC_MTU_1K_BYTES = 0x3,
1944 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1968 u8 reserved_1[0x3];
1983 u8 mtu[0x3];
1987 u8 log_rq_stride[0x3];
2000 u8 reserved_9[0x3];
2010 u8 log_sra_max[0x3];
2012 u8 retry_count[0x3];
2013 u8 rnr_retry[0x3];
2016 u8 cur_rnr_retry[0x3];
2017 u8 cur_retry_count[0x3];
2040 u8 log_rra_max[0x3];
2048 u8 reserved_23[0x3];
2053 u8 reserved_24[0x3];
2068 u8 rq_type[0x3];
2109 u8 reserved_0[0x3];
2191 u8 log_rq_stride[0x3];
2345 u8 log_rq_stride[0x3];
2376 MLX5_SQC_STATE_ERR = 0x3,
2385 u8 min_wqe_inline_mode[0x3];
2445 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2487 MLX5_RQC_STATE_ERR = 0x3,
2525 MLX5_RMPC_STATE_ERR = 0x3,
2549 u8 min_wqe_inline_mode[0x3];
2585 u8 allowed_list_type[0x3];
2606 u8 access_mode_4_2[0x3];
2668 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED = 0x3,
2684 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM = 0x3,
2691 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM = 0x3,
2705 u8 min_wqe_inline_mode[0x3];
2733 u8 lmc[0x3];
2786 u8 reserved_0[0x3];
2796 u8 svlan_pcp[0x3];
2799 u8 cvlan_pcp[0x3];
2830 u8 reserved_6[0x3];
2839 u8 reserved_9[0x3];
2869 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2897 u8 reserved_6[0x3];
2914 u8 mtu[0x3];
2927 u8 eth_prio[0x3];
2959 u8 cqe_sz[0x3];
2976 u8 reserved_6[0x3];
2987 u8 reserved_9[0x3];
3063 u8 reserved_3[0x3];
3677 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
4510 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4549 u8 allowed_list_type[0x3];
7978 u8 proto_mask[0x3];
8159 u8 reserved_0[0x3];
8321 u8 lbf_mode[0x3];
8725 u8 reserved_at_73[0x3];
8727 u8 reserved_at_77[0x3];
8745 u8 port_access_reg_cap_mask_34_to_32[0x3];
9471 u8 reserved_0[0x3];
9474 u8 state[0x3];
9533 u8 prio[0x3];
9536 u8 tclass[0x3];
9545 u8 pprio[0x3];
9570 u8 target[0x3];
9674 u8 log_working_buffer_size[0x3];
9676 u8 reserved_1[0x3];
9911 u8 status[0x3];
9927 u8 status[0x3];
9987 u8 nic_interface_supported[0x3];
10052 u8 prio_tc[0x3];
10408 u8 pwr_status[0x3];
10454 u8 pwr_status[0x3];
10635 u8 trust_state[0x3];