Lines Matching refs:MLX5_PARAM_OFFSET
883 #define MLX5_PARAM_OFFSET(n) \
916 switch (MLX5_PARAM_OFFSET(arg[arg2])) {
917 case MLX5_PARAM_OFFSET(rx_coalesce_usecs):
934 case MLX5_PARAM_OFFSET(rx_coalesce_pkts):
951 case MLX5_PARAM_OFFSET(tx_coalesce_usecs):
968 case MLX5_PARAM_OFFSET(tx_coalesce_pkts):
985 case MLX5_PARAM_OFFSET(tx_queue_size):
1014 case MLX5_PARAM_OFFSET(rx_queue_size):
1045 case MLX5_PARAM_OFFSET(channels_rsss):
1063 case MLX5_PARAM_OFFSET(channels):
1083 case MLX5_PARAM_OFFSET(rx_coalesce_mode):
1103 case MLX5_PARAM_OFFSET(tx_coalesce_mode):
1123 case MLX5_PARAM_OFFSET(hw_lro):
1153 case MLX5_PARAM_OFFSET(cqe_zipping):
1172 case MLX5_PARAM_OFFSET(tx_completion_fact):
1185 case MLX5_PARAM_OFFSET(modify_tx_dma):
1198 case MLX5_PARAM_OFFSET(modify_rx_dma):
1211 case MLX5_PARAM_OFFSET(diag_pci_enable):
1220 case MLX5_PARAM_OFFSET(diag_general_enable):
1229 case MLX5_PARAM_OFFSET(mc_local_lb):
1241 case MLX5_PARAM_OFFSET(uc_local_lb):