Lines Matching refs:cqe
604 struct mlx4_cqe *cqe)
607 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
610 ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome,
611 ((struct mlx4_err_cqe *)cqe)->syndrome);
614 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
732 /* For cpu arch with cache line of 64B the performance is better when cqe size==64B
733 * To enlarge cqe size from 32B to 64B --> 32B of garbage (i.e. 0xccccccc)
734 * was added in the beginning of each cqe (the real data is in the corresponding 32B).
736 * and we get the real cqe data*/
741 struct mlx4_cqe *cqe;
762 * reading 'cqe->index' */
764 cqe = &buf[CQE_FACTOR_INDEX(index, factor)];
767 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
777 if (invalid_cqe(priv, cqe)) {
783 length = be32_to_cpu(cqe->byte_cnt);
801 mb->m_pkthdr.flowid = be32_to_cpu(cqe->immed_rss_invalid);
802 M_HASHTYPE_SET(mb, mlx4_en_rss_hash(cqe->status, udp_rss));
804 if (be32_to_cpu(cqe->vlan_my_qpn) &
806 mb->m_pkthdr.ether_vtag = be16_to_cpu(cqe->sl_vid);
811 (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
812 (cqe->checksum == cpu_to_be16(0xffff))) {
825 if (mlx4_en_can_lro(cqe->status) &&
846 cqe = &buf[CQE_FACTOR_INDEX(index, factor)];