Lines Matching refs:ULL
3233 pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
4242 1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX |\
4243 1ULL << MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB)
4267 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB)) &&
4284 if (pri_addr_path_mask & (1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX)) {
5246 ((1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED) |
5247 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P) |
5248 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED) |
5249 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED) |
5250 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P) |
5251 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED));
5253 u64 qp_path_mask = ((1ULL << MLX4_UPD_QP_PATH_MASK_VLAN_INDEX) |
5254 (1ULL << MLX4_UPD_QP_PATH_MASK_FVL) |
5255 (1ULL << MLX4_UPD_QP_PATH_MASK_CV) |
5256 (1ULL << MLX4_UPD_QP_PATH_MASK_SV) |
5257 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN) |
5258 (1ULL << MLX4_UPD_QP_PATH_MASK_FEUP) |
5259 (1ULL << MLX4_UPD_QP_PATH_MASK_FVL_RX) |
5260 (1ULL << MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE));
5296 upd_context->qp_mask = cpu_to_be64(1ULL << MLX4_UPD_QP_MASK_VSD);
5347 cpu_to_be64(1ULL <<