Lines Matching refs:aq
51 hw->aq.asq.tail = I40E_VF_ATQT1;
52 hw->aq.asq.head = I40E_VF_ATQH1;
53 hw->aq.asq.len = I40E_VF_ATQLEN1;
54 hw->aq.asq.bal = I40E_VF_ATQBAL1;
55 hw->aq.asq.bah = I40E_VF_ATQBAH1;
56 hw->aq.arq.tail = I40E_VF_ARQT1;
57 hw->aq.arq.head = I40E_VF_ARQH1;
58 hw->aq.arq.len = I40E_VF_ARQLEN1;
59 hw->aq.arq.bal = I40E_VF_ARQBAL1;
60 hw->aq.arq.bah = I40E_VF_ARQBAH1;
62 hw->aq.asq.tail = I40E_PF_ATQT;
63 hw->aq.asq.head = I40E_PF_ATQH;
64 hw->aq.asq.len = I40E_PF_ATQLEN;
65 hw->aq.asq.bal = I40E_PF_ATQBAL;
66 hw->aq.asq.bah = I40E_PF_ATQBAH;
67 hw->aq.arq.tail = I40E_PF_ARQT;
68 hw->aq.arq.head = I40E_PF_ARQH;
69 hw->aq.arq.len = I40E_PF_ARQLEN;
70 hw->aq.arq.bal = I40E_PF_ARQBAL;
71 hw->aq.arq.bah = I40E_PF_ARQBAH;
83 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,
85 (hw->aq.num_asq_entries *
91 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf,
92 (hw->aq.num_asq_entries *
95 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
110 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,
112 (hw->aq.num_arq_entries *
128 i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf);
129 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
141 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
160 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head,
161 (hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem)));
164 hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va;
167 for (i = 0; i < hw->aq.num_arq_entries; i++) {
168 bi = &hw->aq.arq.r.arq_bi[i];
171 hw->aq.arq_buf_size,
177 desc = I40E_ADMINQ_DESC(hw->aq.arq, i);
180 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
205 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
206 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
222 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head,
223 (hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem)));
226 hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va;
229 for (i = 0; i < hw->aq.num_asq_entries; i++) {
230 bi = &hw->aq.asq.r.asq_bi[i];
233 hw->aq.asq_buf_size,
245 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
246 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
260 for (i = 0; i < hw->aq.num_arq_entries; i++)
261 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
264 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
267 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
279 for (i = 0; i < hw->aq.num_asq_entries; i++)
280 if (hw->aq.asq.r.asq_bi[i].pa)
281 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
284 i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf);
287 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
290 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
305 wr32(hw, hw->aq.asq.head, 0);
306 wr32(hw, hw->aq.asq.tail, 0);
310 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
313 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
315 wr32(hw, hw->aq.asq.bal, I40E_LO_DWORD(hw->aq.asq.desc_buf.pa));
316 wr32(hw, hw->aq.asq.bah, I40E_HI_DWORD(hw->aq.asq.desc_buf.pa));
319 reg = rd32(hw, hw->aq.asq.bal);
320 if (reg != I40E_LO_DWORD(hw->aq.asq.desc_buf.pa))
338 wr32(hw, hw->aq.arq.head, 0);
339 wr32(hw, hw->aq.arq.tail, 0);
343 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
346 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
348 wr32(hw, hw->aq.arq.bal, I40E_LO_DWORD(hw->aq.arq.desc_buf.pa));
349 wr32(hw, hw->aq.arq.bah, I40E_HI_DWORD(hw->aq.arq.desc_buf.pa));
352 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
355 reg = rd32(hw, hw->aq.arq.bal);
356 if (reg != I40E_LO_DWORD(hw->aq.arq.desc_buf.pa))
368 * in the hw->aq structure:
369 * - hw->aq.num_asq_entries
370 * - hw->aq.arq_buf_size
379 if (hw->aq.asq.count > 0) {
386 if ((hw->aq.num_asq_entries == 0) ||
387 (hw->aq.asq_buf_size == 0)) {
392 hw->aq.asq.next_to_use = 0;
393 hw->aq.asq.next_to_clean = 0;
411 hw->aq.asq.count = hw->aq.num_asq_entries;
431 * in the hw->aq structure:
432 * - hw->aq.num_asq_entries
433 * - hw->aq.arq_buf_size
442 if (hw->aq.arq.count > 0) {
449 if ((hw->aq.num_arq_entries == 0) ||
450 (hw->aq.arq_buf_size == 0)) {
455 hw->aq.arq.next_to_use = 0;
456 hw->aq.arq.next_to_clean = 0;
474 hw->aq.arq.count = hw->aq.num_arq_entries;
494 i40e_acquire_spinlock(&hw->aq.asq_spinlock);
496 if (hw->aq.asq.count == 0) {
502 wr32(hw, hw->aq.asq.head, 0);
503 wr32(hw, hw->aq.asq.tail, 0);
504 wr32(hw, hw->aq.asq.len, 0);
505 wr32(hw, hw->aq.asq.bal, 0);
506 wr32(hw, hw->aq.asq.bah, 0);
508 hw->aq.asq.count = 0; /* to indicate uninitialized queue */
514 i40e_release_spinlock(&hw->aq.asq_spinlock);
528 i40e_acquire_spinlock(&hw->aq.arq_spinlock);
530 if (hw->aq.arq.count == 0) {
536 wr32(hw, hw->aq.arq.head, 0);
537 wr32(hw, hw->aq.arq.tail, 0);
538 wr32(hw, hw->aq.arq.len, 0);
539 wr32(hw, hw->aq.arq.bal, 0);
540 wr32(hw, hw->aq.arq.bah, 0);
542 hw->aq.arq.count = 0; /* to indicate uninitialized queue */
548 i40e_release_spinlock(&hw->aq.arq_spinlock);
559 hw->aq.asq.next_to_use = 0;
560 hw->aq.asq.next_to_clean = 0;
564 hw->aq.arq.next_to_use = 0;
565 hw->aq.arq.next_to_clean = 0;
576 struct i40e_adminq_info *aq = &hw->aq;
582 if (aq->api_maj_ver > 1 ||
583 (aq->api_maj_ver == 1 &&
584 aq->api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710)) {
595 if (aq->api_maj_ver > 1 ||
596 (aq->api_maj_ver == 1 &&
597 aq->api_min_ver >= I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722))
600 if (aq->api_maj_ver > 1 ||
601 (aq->api_maj_ver == 1 &&
602 aq->api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_X722))
605 if (aq->api_maj_ver > 1 ||
606 (aq->api_maj_ver == 1 &&
607 aq->api_min_ver >= I40E_MINOR_VER_FW_REQUEST_FEC_X722))
616 if (aq->api_maj_ver > 1 ||
617 (aq->api_maj_ver == 1 &&
618 aq->api_min_ver >= 5))
621 if (aq->api_maj_ver > 1 ||
622 (aq->api_maj_ver == 1 &&
623 aq->api_min_ver >= 8)) {
628 if (aq->api_maj_ver > 1 ||
629 (aq->api_maj_ver == 1 &&
630 aq->api_min_ver >= 9))
639 * in the hw->aq structure:
640 * - hw->aq.num_asq_entries
641 * - hw->aq.num_arq_entries
642 * - hw->aq.arq_buf_size
643 * - hw->aq.asq_buf_size
647 struct i40e_adminq_info *aq = &hw->aq;
654 if (aq->num_arq_entries == 0 ||
655 aq->num_asq_entries == 0 ||
656 aq->arq_buf_size == 0 ||
657 aq->asq_buf_size == 0) {
661 i40e_init_spinlock(&aq->asq_spinlock);
662 i40e_init_spinlock(&aq->arq_spinlock);
668 hw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT;
689 &aq->fw_maj_ver,
690 &aq->fw_min_ver,
691 &aq->fw_build,
692 &aq->api_maj_ver,
693 &aq->api_min_ver,
723 if (aq->api_maj_ver > I40E_FW_API_VERSION_MAJOR) {
743 i40e_destroy_spinlock(&aq->asq_spinlock);
744 i40e_destroy_spinlock(&aq->arq_spinlock);
763 i40e_destroy_spinlock(&hw->aq.asq_spinlock);
764 i40e_destroy_spinlock(&hw->aq.arq_spinlock);
780 struct i40e_adminq_ring *asq = &(hw->aq.asq);
788 while (rd32(hw, hw->aq.asq.head) != ntc) {
790 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head));
825 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use;
854 i40e_acquire_spinlock(&hw->aq.asq_spinlock);
856 hw->aq.asq_last_status = I40E_AQ_RC_OK;
858 if (hw->aq.asq.count == 0) {
865 val = rd32(hw, hw->aq.asq.head);
866 if (val >= hw->aq.num_asq_entries) {
873 details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);
900 if (buff_size > hw->aq.asq_buf_size) {
933 desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use);
941 dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]);
960 (hw->aq.asq.next_to_use)++;
961 if (hw->aq.asq.next_to_use == hw->aq.asq.count)
962 hw->aq.asq.next_to_use = 0;
964 wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);
980 } while (total_delay < hw->aq.asq_cmd_timeout);
1007 hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval;
1014 /* save writeback aq if requested */
1022 if (rd32(hw, hw->aq.asq.len) & I40E_GL_ATQLEN_ATQCRIT_MASK) {
1034 i40e_release_spinlock(&hw->aq.asq_spinlock);
1070 u16 ntc = hw->aq.arq.next_to_clean;
1082 i40e_acquire_spinlock(&hw->aq.arq_spinlock);
1084 if (hw->aq.arq.count == 0) {
1093 ntu = rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK;
1095 ntu = rd32(hw, hw->aq.arq.head) & I40E_VF_ARQH1_ARQH_MASK;
1103 desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);
1106 hw->aq.arq_last_status =
1114 hw->aq.arq_last_status);
1123 hw->aq.arq.r.arq_bi[desc_idx].va,
1128 hw->aq.arq_buf_size);
1134 bi = &hw->aq.arq.r.arq_bi[ntc];
1138 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
1145 wr32(hw, hw->aq.arq.tail, ntc);
1148 if (ntc == hw->aq.num_arq_entries)
1150 hw->aq.arq.next_to_clean = ntc;
1151 hw->aq.arq.next_to_use = ntu;
1157 *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc);
1159 i40e_release_spinlock(&hw->aq.arq_spinlock);