Lines Matching refs:x7
1441 #define IXGBE_RQTC_TC0_MASK (0x7 << 0)
1442 #define IXGBE_RQTC_TC1_MASK (0x7 << 4)
1443 #define IXGBE_RQTC_TC2_MASK (0x7 << 8)
1444 #define IXGBE_RQTC_TC3_MASK (0x7 << 12)
1445 #define IXGBE_RQTC_TC4_MASK (0x7 << 16)
1446 #define IXGBE_RQTC_TC5_MASK (0x7 << 20)
1447 #define IXGBE_RQTC_TC6_MASK (0x7 << 24)
1448 #define IXGBE_RQTC_TC7_MASK (0x7 << 28)
1451 #define IXGBE_PSRTYPE_RQPL_MASK 0x7
1547 #define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7
1633 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK 0x7 /* Speed/Duplex Mask */
1642 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL 0x7 /* 10Gb/s Full Duplex */
2173 #define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT)
2174 #define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
2180 #define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
2430 #define IXGBE_FW_PATCH_VERSION_4 0x7
2440 #define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt WWNN prefix offset */
2455 #define IXGBE_X540_FW_PATCH_VERSION_4 0x7
3511 IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7,
4269 #define BYPASS_WDT_32 0x7
4341 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10M ~(0x7 << 28)
4346 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_2_5G (0x7 << 28)
4347 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK (0x7 << 28)
4353 #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK (0x7 << 8)
4410 #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK 0x7