Lines Matching refs:BIU_BLOCK
62 #define BIU_BLOCK (0 << _BLK_REG_SHFT)
89 #define BIU2400_FLASH_ADDR (BIU_BLOCK+0x00) /* Flash Access Address */
90 #define BIU2400_FLASH_DATA (BIU_BLOCK+0x04) /* Flash Data */
91 #define BIU2400_CSR (BIU_BLOCK+0x08) /* ISP Control/Status */
92 #define BIU2400_ICR (BIU_BLOCK+0x0C) /* ISP to PCI Interrupt Control */
93 #define BIU2400_ISR (BIU_BLOCK+0x10) /* ISP to PCI Interrupt Status */
95 #define BIU2400_REQINP (BIU_BLOCK+0x1C) /* Request Queue In */
96 #define BIU2400_REQOUTP (BIU_BLOCK+0x20) /* Request Queue Out */
97 #define BIU2400_RSPINP (BIU_BLOCK+0x24) /* Response Queue In */
98 #define BIU2400_RSPOUTP (BIU_BLOCK+0x28) /* Response Queue Out */
100 #define BIU2400_PRI_REQINP (BIU_BLOCK+0x2C) /* Priority Request Q In */
101 #define BIU2400_PRI_REQOUTP (BIU_BLOCK+0x30) /* Priority Request Q Out */
103 #define BIU2400_ATIO_RSPINP (BIU_BLOCK+0x3C) /* ATIO Queue In */
104 #define BIU2400_ATIO_RSPOUTP (BIU_BLOCK+0x40) /* ATIO Queue Out */
106 #define BIU2400_R2HSTS (BIU_BLOCK+0x44) /* RISC to Host Status */
108 #define BIU2400_HCCR (BIU_BLOCK+0x48) /* Host Command and Control Status */
109 #define BIU2400_GPIOD (BIU_BLOCK+0x4C) /* General Purpose I/O Data */
110 #define BIU2400_GPIOE (BIU_BLOCK+0x50) /* General Purpose I/O Enable */
111 #define BIU2400_IOBBA (BIU_BLOCK+0x54) /* I/O Bus Base Address */
112 #define BIU2400_HSEMA (BIU_BLOCK+0x58) /* Host-to-Host Semaphore */