Lines Matching refs:reg_read
166 reg_read(ig4iic_softc_t *sc, uint32_t reg)
190 reg_read(sc, IG4_REG_CLR_RX_UNDER);
192 reg_read(sc, IG4_REG_CLR_RX_OVER);
194 reg_read(sc, IG4_REG_CLR_TX_OVER);
197 src = reg_read(sc, IG4_REG_TX_ABRT_SOURCE);
198 reg_read(sc, IG4_REG_CLR_TX_ABORT);
250 reg_read(sc, IG4_REG_CLR_INTR);
256 v = reg_read(sc, IG4_REG_ENABLE_STATUS);
282 v = reg_read(sc, IG4_REG_RAW_INTR_STAT);
293 v = reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK;
355 ctl = reg_read(sc, IG4_REG_CTL);
384 reg_read(sc, IG4_REG_CLR_INTR);
397 return ((reg_read(sc, IG4_REG_RAW_INTR_STAT) &
440 (reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK);
466 reg_read(sc, IG4_REG_RXFLR) & IG4_FIFOLVL_MASK);
470 reg_read(sc, IG4_REG_DATA_CMD);
497 (reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK);
614 reg_read(sc, IG4_REG_CLR_TX_ABORT);
646 reg_read(sc, IG4_REG_CLR_INTR);
661 while (reg_read(sc, IG4_REG_I2C_STA) &
663 reg_read(sc, IG4_REG_DATA_CMD);
664 reg_read(sc, IG4_REG_TX_ABRT_SOURCE);
665 reg_read(sc, IG4_REG_CLR_INTR);
829 sc->cfg.version = reg_read(sc, IG4_REG_COMP_VER);
830 sc->cfg.bus_speed = reg_read(sc, IG4_REG_CTL) & IG4_CTL_SPEED_MASK;
832 reg_read(sc, IG4_REG_SS_SCL_HCNT) & IG4_SCL_CLOCK_MASK;
834 reg_read(sc, IG4_REG_SS_SCL_LCNT) & IG4_SCL_CLOCK_MASK;
836 reg_read(sc, IG4_REG_FS_SCL_HCNT) & IG4_SCL_CLOCK_MASK;
838 reg_read(sc, IG4_REG_FS_SCL_LCNT) & IG4_SCL_CLOCK_MASK;
840 reg_read(sc, IG4_REG_SDA_HOLD) & IG4_SDA_TX_HOLD_MASK;
847 v = reg_read(sc, IG4_REG_COMP_PARAM1);
859 v = reg_read(sc, IG4_REG_TX_TL);
862 (reg_read(sc, IG4_REG_TX_TL) & IG4_FIFO_MASK) + 1;
864 v = reg_read(sc, IG4_REG_RX_TL);
867 (reg_read(sc, IG4_REG_RX_TL) & IG4_FIFO_MASK) + 1;
930 v = reg_read(sc, IG4_REG_DEVIDLE_CTRL);
947 v = reg_read(sc, IG4_REG_COMP_TYPE);
950 v = reg_read(sc, IG4_REG_COMP_PARAM1);
951 v = reg_read(sc, IG4_REG_GENERAL);
960 v = reg_read(sc, IG4_REG_GENERAL);
965 v = reg_read(sc, IG4_REG_SW_LTR_VALUE);
966 v = reg_read(sc, IG4_REG_AUTO_LTR_VALUE);
968 v = reg_read(sc, IG4_REG_ACTIVE_LTR_VALUE);
969 v = reg_read(sc, IG4_REG_IDLE_LTR_VALUE);
973 v = reg_read(sc, IG4_REG_COMP_VER);
983 reg_read(sc, IG4_REG_CLR_INTR);
1150 if (sc->intr_mask != 0 && reg_read(sc, IG4_REG_INTR_STAT) != 0) {
1162 device_printf(sc->dev, " %-23s %08x\n", #reg, reg_read(sc, reg))