Lines Matching defs:phy_type_low
202 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
203 (unsigned long long)LE64_TO_CPU(pcaps->phy_type_low));
226 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
298 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
302 if (hw_link_info->phy_type_low) {
308 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII &&
315 switch (hw_link_info->phy_type_low) {
453 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);
481 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
482 (unsigned long long)li->phy_type_low);
2568 * @phy_type_low: lower part of phy_type
2572 * [phy_type_low, phy_type_high] to its corresponding link speed.
2573 * Note: In the structure of [phy_type_low, phy_type_high], there should
2580 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2585 switch (phy_type_low) {
2701 * @phy_type_low: pointer to the lower part of phy_type
2709 * Each entry in this [phy_type_low, phy_type_high] structure will
2711 * in [phy_type_low, phy_type_high] structure based on the value of
2715 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
2729 *phy_type_low |= BIT_ULL(index);
2777 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
2778 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low));
3099 if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
3129 cfg->phy_type_low = caps->phy_type_low;
5136 ldo->phy_type_low |= ((u64)buf << (i * 16));