Lines Matching refs:MIPS_CTR_1
62 { PMC_EV_MIPS74K_JR_31_MISPREDICTIONS, MIPS_CTR_1, 2 },
64 { PMC_EV_MIPS74K_JR_31_NO_PREDICTIONS, MIPS_CTR_1, 3 },
66 { PMC_EV_MIPS74K_ITLB_MISSES, MIPS_CTR_1, 4 },
67 { PMC_EV_MIPS74K_JTLB_INSN_MISSES, MIPS_CTR_1, 5 },
69 { PMC_EV_MIPS74K_ICACHE_MISSES, MIPS_CTR_1, 6 },
72 { PMC_EV_MIPS74K_PDTRACE_BACK_STALLS, MIPS_CTR_1, 8 },
74 { PMC_EV_MIPS74K_KILLED_FETCH_SLOTS, MIPS_CTR_1, 9 },
76 { PMC_EV_MIPS74K_IFU_IDU_NO_FETCH_CYCLES, MIPS_CTR_1, 11 },
79 { PMC_EV_MIPS74K_DDQ1_FULL_DR_STALLS, MIPS_CTR_1, 13 },
81 { PMC_EV_MIPS74K_AGCB_FULL_DR_STALLS, MIPS_CTR_1, 14 },
83 { PMC_EV_MIPS74K_IODQ_FULL_DR_STALLS, MIPS_CTR_1, 15 },
85 { PMC_EV_MIPS74K_AGEN_EMPTY_CYCLES, MIPS_CTR_1, 16 },
87 { PMC_EV_MIPS74K_AGEN_OPERANDS_NOT_READY_CYCLES, MIPS_CTR_1, 17 },
89 { PMC_EV_MIPS74K_AGEN_NO_ISSUES_CYCLES, MIPS_CTR_1, 18 },
91 { PMC_EV_MIPS74K_AGEN_BUBBLE_CYCLES, MIPS_CTR_1, 19 },
93 { PMC_EV_MIPS74K_DUAL_ISSUE_CYCLES, MIPS_CTR_1, 20 },
95 { PMC_EV_MIPS74K_OOO_AGEN_ISSUE_CYCLES, MIPS_CTR_1, 21 },
97 { PMC_EV_MIPS74K_DCACHE_LINE_REFILL_REQUESTS, MIPS_CTR_1, 22 },
99 { PMC_EV_MIPS74K_DCACHE_ACCESSES, MIPS_CTR_1, 23 },
101 { PMC_EV_MIPS74K_DCACHE_MISSES, MIPS_CTR_1, 24 },
103 { PMC_EV_MIPS74K_JTLB_DATA_MISSES, MIPS_CTR_1, 25 },
105 { PMC_EV_MIPS74K_VA_TRANSALTION_CORNER_CASES, MIPS_CTR_1, 26 },
107 { PMC_EV_MIPS74K_LOAD_STORE_NO_FILL_REQUESTS, MIPS_CTR_1, 27 },
109 { PMC_EV_MIPS74K_L2_CACHE_ACCESSES, MIPS_CTR_1, 28 },
111 { PMC_EV_MIPS74K_L2_CACHE_MISS_CYCLES, MIPS_CTR_1, 29 },
113 { PMC_EV_MIPS74K_FSB_OVER_50_FULL, MIPS_CTR_1, 30 },
115 { PMC_EV_MIPS74K_LDQ_OVER_50_FULL, MIPS_CTR_1, 31 },
117 { PMC_EV_MIPS74K_WBB_OVER_50_FULL, MIPS_CTR_1, 32 },
119 { PMC_EV_MIPS74K_CP1_CP2_LOAD_INSNS, MIPS_CTR_1, 35 },
121 { PMC_EV_MIPS74K_MISPREDICTED_JR_31_INSNS, MIPS_CTR_1, 36 },
123 { PMC_EV_MIPS74K_CP1_CP2_COND_BRANCH_INSNS, MIPS_CTR_1, 37 },
125 { PMC_EV_MIPS74K_MISPREDICTED_BRANCH_LIKELY_INSNS, MIPS_CTR_1, 38 },
127 { PMC_EV_MIPS74K_MISPREDICTED_BRANCH_INSNS, MIPS_CTR_1, 39 },
129 { PMC_EV_MIPS74K_FPU_INSNS, MIPS_CTR_1, 40 },
131 { PMC_EV_MIPS74K_STORE_INSNS, MIPS_CTR_1, 41 },
133 { PMC_EV_MIPS74K_MIPS16_INSNS, MIPS_CTR_1, 42 },
135 { PMC_EV_MIPS74K_NT_MUL_DIV_INSNS, MIPS_CTR_1, 43 },
137 { PMC_EV_MIPS74K_ALU_DSP_SATURATION_INSNS, MIPS_CTR_1, 44 },
139 { PMC_EV_MIPS74K_MDU_DSP_SATURATION_INSNS, MIPS_CTR_1, 45 },
141 { PMC_EV_MIPS74K_UNCACHED_STORE_INSNS, MIPS_CTR_1, 46 },
145 { PMC_EV_MIPS74K_FAILED_SC_INSNS, MIPS_CTR_1, 51 },
147 { PMC_EV_MIPS74K_CACHE_HIT_PREFETCH_INSNS, MIPS_CTR_1, 52 },
149 { PMC_EV_MIPS74K_LOAD_MISS_INSNS, MIPS_CTR_1, 53 },
151 { PMC_EV_MIPS74K_TWO_INSNS_CYCLES, MIPS_CTR_1, 54 },
153 { PMC_EV_MIPS74K_CP1_CP2_STORE_INSNS, MIPS_CTR_1, 55 },
157 { PMC_EV_MIPS74K_GRADUATION_REPLAYS, MIPS_CTR_1, 58 },
160 { PMC_EV_MIPS74K_DSPRAM_EVENTS, MIPS_CTR_1, 62 },
163 { PMC_EV_MIPS74K_SYSTEM_EVENT_1, MIPS_CTR_1, 64 },
165 { PMC_EV_MIPS74K_SYSTEM_EVENT_3, MIPS_CTR_1, 65 },
167 { PMC_EV_MIPS74K_SYSTEM_EVENT_5, MIPS_CTR_1, 66 },
169 { PMC_EV_MIPS74K_SYSTEM_EVENT_7, MIPS_CTR_1, 67 },
171 { PMC_EV_MIPS74K_OCP_ALL_CACHEABLE_REQUESTS, MIPS_CTR_1, 68 },
173 { PMC_EV_MIPS74K_OCP_READ_CACHEABLE_REQUESTS, MIPS_CTR_1, 69 },
175 { PMC_EV_MIPS74K_OCP_WRITE_CACHEABLE_REQUESTS, MIPS_CTR_1, 70 },
177 { PMC_EV_MIPS74K_FSB_25_50_FULL, MIPS_CTR_1, 74 },
179 { PMC_EV_MIPS74K_LDQ_25_50_FULL, MIPS_CTR_1, 75 },
181 { PMC_EV_MIPS74K_WBB_25_50_FULL, MIPS_CTR_1, 76 },