Lines Matching refs:hal
166 val = sc->hal.mtkswitch_read(sc, MTKSWITCH_REG32(reg));
178 tmp = sc->hal.mtkswitch_read(sc, MTKSWITCH_REG32(reg));
186 sc->hal.mtkswitch_write(sc, MTKSWITCH_REG32(reg), tmp);
229 val = sc->hal.mtkswitch_read(sc, MTKSWITCH_PCR(port));
231 sc->hal.mtkswitch_write(sc, MTKSWITCH_PCR(port), val);
234 val = sc->hal.mtkswitch_read(sc, MTKSWITCH_PVC(port));
236 sc->hal.mtkswitch_write(sc, MTKSWITCH_PVC(port), val);
243 sc->hal.mtkswitch_write(sc, MTKSWITCH_PMCR(port), val);
253 val = sc->hal.mtkswitch_read(sc, MTKSWITCH_PMSR(port));
281 while (sc->hal.mtkswitch_read(sc, MTKSWITCH_ATC) & ATC_BUSY);
282 sc->hal.mtkswitch_write(sc, MTKSWITCH_ATC, ATC_BUSY |
284 while (sc->hal.mtkswitch_read(sc, MTKSWITCH_ATC) & ATC_BUSY);
307 err = sc->hal.mtkswitch_vlan_set_pvid(sc, p->es_port,
328 sc->hal.mtkswitch_vlan_get_pvid(sc, p->es_port, &p->es_pvid);
345 while (sc->hal.mtkswitch_read(sc, MTKSWITCH_VTCR) & VTCR_BUSY);
346 sc->hal.mtkswitch_write(sc, MTKSWITCH_VTCR, VTCR_BUSY |
348 while (sc->hal.mtkswitch_read(sc, MTKSWITCH_VTCR) & VTCR_BUSY);
362 val = sc->hal.mtkswitch_read(sc, MTKSWITCH_VTIM(i));
365 sc->hal.mtkswitch_write(sc, MTKSWITCH_VTIM(i), val);
380 sc->hal.mtkswitch_write(sc, MTKSWITCH_VAWD1, val);
381 sc->hal.mtkswitch_write(sc, MTKSWITCH_VAWD2, 0);
383 sc->hal.mtkswitch_write(sc, MTKSWITCH_VTCR, val);
387 sc->hal.mtkswitch_vlan_set_pvid(sc, i, 1);
413 v->es_vid = (sc->hal.mtkswitch_read(sc,
420 while (sc->hal.mtkswitch_read(sc, MTKSWITCH_VTCR) & VTCR_BUSY);
421 sc->hal.mtkswitch_write(sc, MTKSWITCH_VTCR, VTCR_BUSY |
423 while ((val = sc->hal.mtkswitch_read(sc, MTKSWITCH_VTCR)) & VTCR_BUSY);
429 val = sc->hal.mtkswitch_read(sc, MTKSWITCH_VAWD1);
438 val = sc->hal.mtkswitch_read(sc, MTKSWITCH_VAWD2);
464 while (sc->hal.mtkswitch_read(sc, MTKSWITCH_VTCR) & VTCR_BUSY);
466 val = sc->hal.mtkswitch_read(sc,
470 sc->hal.mtkswitch_write(sc, MTKSWITCH_VTIM(v->es_vlangroup),
479 sc->hal.mtkswitch_write(sc, MTKSWITCH_VAWD1, val);
486 sc->hal.mtkswitch_write(sc, MTKSWITCH_VAWD2, val);
489 sc->hal.mtkswitch_write(sc, MTKSWITCH_VTCR, VTCR_BUSY |
491 while ((val = sc->hal.mtkswitch_read(sc, MTKSWITCH_VTCR)) & VTCR_BUSY);
507 *pvid = sc->hal.mtkswitch_read(sc, MTKSWITCH_PPBV1(port));
520 sc->hal.mtkswitch_write(sc, MTKSWITCH_PPBV1(port), val);
521 sc->hal.mtkswitch_write(sc, MTKSWITCH_PPBV2(port), val);
539 sc->hal.mtkswitch_read = mtkswitch_reg_read32_mt7621;
540 sc->hal.mtkswitch_write = mtkswitch_reg_write32_mt7621;
543 sc->hal.mtkswitch_read = mtkswitch_reg_read32;
544 sc->hal.mtkswitch_write = mtkswitch_reg_write32;
547 sc->hal.mtkswitch_reset = mtkswitch_reset;
548 sc->hal.mtkswitch_hw_setup = mtkswitch_hw_setup;
549 sc->hal.mtkswitch_hw_global_setup = mtkswitch_hw_global_setup;
550 sc->hal.mtkswitch_port_init = mtkswitch_port_init;
551 sc->hal.mtkswitch_get_port_status = mtkswitch_get_port_status;
552 sc->hal.mtkswitch_atu_flush = mtkswitch_atu_flush;
553 sc->hal.mtkswitch_port_vlan_setup = mtkswitch_port_vlan_setup;
554 sc->hal.mtkswitch_port_vlan_get = mtkswitch_port_vlan_get;
555 sc->hal.mtkswitch_vlan_init_hw = mtkswitch_vlan_init_hw;
556 sc->hal.mtkswitch_vlan_getvgroup = mtkswitch_vlan_getvgroup;
557 sc->hal.mtkswitch_vlan_setvgroup = mtkswitch_vlan_setvgroup;
558 sc->hal.mtkswitch_vlan_get_pvid = mtkswitch_vlan_get_pvid;
559 sc->hal.mtkswitch_vlan_set_pvid = mtkswitch_vlan_set_pvid;
560 sc->hal.mtkswitch_phy_read = mtkswitch_phy_read;
561 sc->hal.mtkswitch_phy_write = mtkswitch_phy_write;
562 sc->hal.mtkswitch_reg_read = mtkswitch_reg_read;
563 sc->hal.mtkswitch_reg_write = mtkswitch_reg_write;