Lines Matching defs:phy
90 struct e1000_phy_info *phy = &hw->phy;
95 if (hw->phy.media_type != e1000_media_type_copper) {
96 phy->type = e1000_phy_none;
99 phy->ops.power_up = e1000_power_up_phy_copper;
100 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
103 phy->addr = 1;
104 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
105 phy->reset_delay_us = 100;
106 phy->type = e1000_phy_gg82563;
108 phy->ops.acquire = e1000_acquire_phy_80003es2lan;
109 phy->ops.check_polarity = e1000_check_polarity_m88;
110 phy->ops.check_reset_block = e1000_check_reset_block_generic;
111 phy->ops.commit = e1000_phy_sw_reset_generic;
112 phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan;
113 phy->ops.get_info = e1000_get_phy_info_m88;
114 phy->ops.release = e1000_release_phy_80003es2lan;
115 phy->ops.reset = e1000_phy_hw_reset_generic;
116 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
118 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan;
119 phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan;
120 phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan;
121 phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan;
123 phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan;
128 /* Verify phy id */
129 if (phy->id != GG82563_E_PHY_ID)
204 hw->phy.media_type = e1000_media_type_internal_serdes;
210 hw->phy.media_type = e1000_media_type_copper;
267 /* set lan id for port to determine which phy lock to use */
285 hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan;
557 * This is a function pointer entry point called by the phy module.
588 * function pointer entry point called by the phy module.
598 if (!(hw->phy.ops.read_reg))
604 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
609 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
615 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data);
621 /* Reset the phy to commit changes. */
624 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data);
630 if (hw->phy.autoneg_wait_to_complete) {
631 DEBUGOUT("Waiting for forced speed/duplex link on GG82563 phy.\n");
654 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
659 /* Resetting the phy means we need to verify the TX_CLK corresponds
672 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
683 * This is a function pointer entry point called by the phy module.
687 struct e1000_phy_info *phy = &hw->phy;
693 if (!(hw->phy.ops.read_reg))
696 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
705 phy->min_cable_length = e1000_gg82563_cable_length_table[index];
706 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
708 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
728 if (hw->phy.media_type == e1000_media_type_copper) {
731 hw->phy.ops.cfg_on_link_up(hw);
941 if (hw->phy.media_type != e1000_media_type_copper)
971 struct e1000_phy_info *phy = &hw->phy;
978 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
986 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
997 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data);
1003 switch (phy->mdix) {
1023 if (phy->disable_polarity_correction)
1026 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data);
1031 ret_val = hw->phy.ops.commit(hw);
1054 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1059 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data);
1067 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1078 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1083 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1089 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1098 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data);
1103 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data);
1132 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1184 if (hw->phy.media_type == e1000_media_type_copper) {
1231 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1236 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1248 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1282 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1287 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1296 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1402 hw->phy.ops.check_reset_block(hw)))