Lines Matching refs:T5
162 /* T5 bus driver interface */
183 /* T5 port (cxl) interface */
190 /* T5 VI (vcxl) interface */
247 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
267 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to
268 * T5 are under hw.cxl.
273 "cxgbe(4) T5+ parameters");
985 * The T5 chips do not properly echo the No Snoop and Relaxed
3043 /* T5+ use the relative offset inside the PCIe BAR */
3731 .fw_ver = htobe32(FW_VERSION(T5)),
3732 .intfver_nic = FW_INTFVER(T5, NIC),
3733 .intfver_vnic = FW_INTFVER(T5, VNIC),
3734 .intfver_ofld = FW_INTFVER(T5, OFLD),
3735 .intfver_ri = FW_INTFVER(T5, RI),
3736 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
3737 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
3738 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
3739 .intfver_fcoe = FW_INTFVER(T5, FCOE),
7951 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */
8794 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */
11805 sx_init(&t4_list_lock, "T4/T5 adapters");
11809 sx_init(&t4_uld_list_lock, "T4/T5 ULDs");