Lines Matching refs:err
103 int err;
105 for (err = 0; rv->mmd_addr && !err; rv++) {
107 err = mdio_write(phy, rv->mmd_addr, rv->reg_addr,
110 err = t3_mdio_change_bits(phy, rv->mmd_addr,
114 return err;
131 int i, err;
134 err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL_I2C_CTRL,
136 if (err)
137 return err;
141 err = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL_I2C_STAT, &stat);
142 if (err)
143 return err;
145 err = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL_I2C_DATA,
147 if (err)
148 return err;
162 int i, err;
165 err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL_I2C_DATA, data);
166 if (err)
167 return err;
169 err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL_I2C_CTRL,
171 if (err)
172 return err;
176 err = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL_I2C_STAT, &stat);
177 if (err)
178 return err;
238 int err;
240 err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL100X_TX_DISABLE, !!enable);
241 if (!err)
242 err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR,
244 return err;
261 int err;
263 if ((err = ael1002_power_down(phy, 0)) ||
264 (err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL100X_TX_CONFIG1, 1)) ||
265 (err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL1002_PWR_DOWN_HI, 0)) ||
266 (err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL1002_PWR_DOWN_LO, 0)) ||
267 (err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL1002_XFI_EQL, 0x18)) ||
268 (err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, AEL1002_LB_EN,
270 return err;
272 err = ael1002_get_module_type(phy, 300);
273 if (err >= 0)
274 phy->modtype = err;
292 int err = mdio_read(phy, MDIO_DEV_PMA_PMD, PMD_RSD, &stat0);
294 if (!err)
295 err = mdio_read(phy, MDIO_DEV_PCS, PCS_STAT1_R, &stat1);
296 if (!err)
297 err = mdio_read(phy, MDIO_DEV_XGXS, XS_LN_STAT, &stat2);
298 if (err)
299 return err;
348 int err;
357 err = ael1002_get_module_type(phy, 0);
358 if (err >= 0)
359 phy->modtype = err;
366 int err;
368 err = t3_phy_reset(phy, MDIO_DEV_PMA_PMD, wait);
369 if (err)
370 return err;
382 err = t3_phy_reset(phy, MDIO_DEV_PMA_PMD, wait);
383 if (err)
384 return err;
388 err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR, 1, 1);
389 if (err)
390 return err;
394 err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR, 1, 0);
396 return err;
807 int i, err;
809 err = set_phy_regs(phy, regs);
810 if (err)
811 return err;
815 for (i = 0; i < ARRAY_SIZE(sr_edc) && !err; i += 2)
816 err = mdio_write(phy, MDIO_DEV_PMA_PMD, sr_edc[i],
818 if (!err)
820 return err;
1202 int i, err;
1204 err = set_phy_regs(phy, regs);
1205 if (!err && modtype == phy_modtype_twinax_long)
1206 err = set_phy_regs(phy, preemphasis);
1207 if (err)
1208 return err;
1212 for (i = 0; i < ARRAY_SIZE(twinax_edc) && !err; i += 2)
1213 err = mdio_write(phy, MDIO_DEV_PMA_PMD, twinax_edc[i],
1215 if (!err)
1217 return err;
1237 int err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL2005_GPIO_CTRL, 0x200);
1238 return err ? err : t3_phy_lasi_intr_enable(phy);
1243 int err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL2005_GPIO_CTRL, 0x100);
1244 return err ? err : t3_phy_lasi_intr_disable(phy);
1249 int err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL2005_GPIO_CTRL, 0xd00);
1250 return err ? err : t3_phy_lasi_intr_clear(phy);
1271 int err;
1274 err = mdio_read(phy, MDIO_DEV_PMA_PMD, LASI_CTRL, &lasi_ctrl);
1275 if (err)
1276 return err;
1278 err = t3_phy_reset(phy, MDIO_DEV_PMA_PMD, 0);
1279 if (err)
1280 return err;
1284 err = set_phy_regs(phy, regs0);
1285 if (err)
1286 return err;
1290 err = ael2005_get_module_type(phy, 0);
1291 if (err < 0)
1292 return err;
1293 phy->modtype = (u8)err;
1295 if (err == phy_modtype_none)
1296 err = 0;
1297 else if (err == phy_modtype_twinax || err == phy_modtype_twinax_long)
1298 err = ael2005_setup_twinax_edc(phy, err);
1300 err = ael2005_setup_sr_edc(phy);
1301 if (err)
1302 return err;
1304 err = set_phy_regs(phy, regs1);
1305 if (err)
1306 return err;
1310 err = ael2005_intr_enable(phy);
1311 return err;
1388 int err;
1397 err = ael2005_get_module_type(phy, 0);
1398 if (err >= 0)
1399 phy->modtype = err;
1420 int err;
1422 err = set_phy_regs(phy, regs);
1424 if (err)
1425 return err;
1894 int i, err;
1897 err = set_phy_regs(phy, uCclock40MHz);
1899 if (err)
1900 return err;
1901 err = set_phy_regs(phy, uCclockActivate);
1903 if (err)
1904 return err;
1906 for (i = 0; i < ARRAY_SIZE(twinax_edc) && !err; i += 2)
1907 err = mdio_write(phy, MDIO_DEV_PMA_PMD, twinax_edc[i],
1910 err = set_phy_regs(phy, uCactivate);
1911 if (!err)
1913 return err;
1954 int err;
1956 err = set_phy_regs(phy, regs);
1957 if (err)
1958 return err;
1961 err = t3_phy_lasi_intr_enable(phy);
1962 if (err)
1963 return err;
1983 int err;
1985 err = set_phy_regs(phy, regs);
1986 if (err)
1987 return err;
1999 int err = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL2020_GPIO_INTR, &stat);
2000 return err ? err : t3_phy_lasi_intr_clear(phy);
2028 int err;
2032 err = mdio_read(phy, MDIO_DEV_PMA_PMD, LASI_CTRL, &lasi_ctrl);
2033 if (err)
2034 return err;
2036 err = t3_phy_reset(phy, MDIO_DEV_PMA_PMD, 125);
2037 if (err)
2038 return err;
2043 err = set_phy_regs(phy, ael2020_reset_regs);
2044 if (err)
2045 return err;
2049 err = ael2020_get_module_type(phy, 0);
2050 if (err < 0)
2051 return err;
2052 phy->modtype = (u8)err;
2053 if (err == phy_modtype_none)
2054 err = 0;
2055 else if (err == phy_modtype_twinax || err == phy_modtype_twinax_long)
2056 err = ael2020_setup_twinax_edc(phy, err);
2058 err = ael2020_setup_sr_edc(phy);
2059 if (err)
2060 return err;
2064 err = ael2020_intr_enable(phy);
2065 return err;
2140 int err;
2148 err = set_phy_regs(phy, ael2020_reset_regs);
2149 if (err)
2150 return err;
2153 err = ael2020_get_module_type(phy, 0);
2154 if (err >= 0)
2155 phy->modtype = err;
2169 int err = mdio_read(phy, MDIO_DEV_PMA_PMD, PMD_RSD, &stat0);
2171 if (!err)
2172 err = mdio_read(phy, MDIO_DEV_PCS, PCS_STAT1_X, &stat1);
2173 if (!err)
2174 err = mdio_read(phy, MDIO_DEV_XGXS, XS_LN_STAT, &stat2);
2175 if (err)
2176 return err;