Lines Matching refs:CAS_WRITE_4
333 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_MII);
344 CAS_WRITE_4(sc, CAS_MIF_CONF, v);
349 CAS_WRITE_4(sc, CAS_SATURN_PCFG,
366 CAS_WRITE_4(sc, CAS_MIF_CONF, v);
371 CAS_WRITE_4(sc, CAS_SATURN_PCFG,
387 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_SERDES);
391 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 0);
395 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, CAS_PCS_SERDES_CTRL_ESD);
398 CAS_WRITE_4(sc, CAS_PCS_CONF, CAS_PCS_CONF_EN);
663 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0);
664 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0);
665 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0);
666 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0);
667 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0);
668 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0);
669 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0);
670 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0);
704 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff);
713 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX |
736 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff);
775 CAS_WRITE_4(sc, CAS_RX_CONF, 0);
782 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX |
802 CAS_WRITE_4(sc, CAS_TX_CONF, 0);
809 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_TX |
824 CAS_WRITE_4(sc, CAS_MAC_RX_CONF,
839 CAS_WRITE_4(sc, CAS_MAC_TX_CONF,
1012 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_HI,
1014 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_LO,
1017 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_HI,
1019 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_LO,
1022 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_HI,
1024 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_LO,
1028 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_HI,
1030 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_LO,
1044 CAS_WRITE_4(sc, CAS_CAW, CAS_CAW_RR_DIS);
1050 CAS_WRITE_4(sc, CAS_INF_BURST,
1055 CAS_WRITE_4(sc, CAS_INTMASK,
1066 CAS_WRITE_4(sc, CAS_CLEAR_ALIAS, 0);
1067 CAS_WRITE_4(sc, CAS_MAC_RX_MASK, ~CAS_MAC_RX_OVERFLOW);
1068 CAS_WRITE_4(sc, CAS_MAC_TX_MASK,
1071 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK,
1075 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK,
1081 CAS_WRITE_4(sc, CAS_ERROR_MASK,
1086 CAS_WRITE_4(sc, CAS_BIM_CONF,
1094 CAS_WRITE_4(sc, CAS_TX_CONF, v | CAS_TX_CONF_TXDMA_EN |
1107 CAS_WRITE_4(sc, CAS_RX_CONF,
1111 CAS_WRITE_4(sc, CAS_RX_PTHRS,
1115 CAS_WRITE_4(sc, CAS_RX_BLANK,
1119 CAS_WRITE_4(sc, CAS_RX_AEMPTY_THRS,
1123 CAS_WRITE_4(sc, CAS_RX_PSZ,
1130 CAS_WRITE_4(sc, CAS_RX_RED, 0);
1134 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_ADDR, v);
1135 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_LO, 0);
1136 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_MD, 0);
1137 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_HI, 0);
1141 CAS_WRITE_4(sc, CAS_RX_CTRL_FIFO, 0);
1142 CAS_WRITE_4(sc, CAS_RX_IPP_ADDR, 0);
1145 CAS_WRITE_4(sc, CAS_RX_CONF,
1165 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, v);
1170 CAS_WRITE_4(sc, CAS_RX_KICK, CAS_NRXDESC - 4);
1171 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, 0);
1173 CAS_WRITE_4(sc, CAS_RX_KICK2, CAS_NRXDESC2 - 4);
1338 CAS_WRITE_4(sc, CAS_MAC_IPG0, 0);
1339 CAS_WRITE_4(sc, CAS_MAC_IPG1, 8);
1340 CAS_WRITE_4(sc, CAS_MAC_IPG2, 4);
1343 CAS_WRITE_4(sc, CAS_MAC_MIN_FRAME, ETHER_MIN_LEN);
1345 CAS_WRITE_4(sc, CAS_MAC_MAX_BF,
1351 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7);
1352 CAS_WRITE_4(sc, CAS_MAC_JAM_SIZE, 0x4);
1353 CAS_WRITE_4(sc, CAS_MAC_ATTEMPT_LIMIT, 0x10);
1354 CAS_WRITE_4(sc, CAS_MAC_CTRL_TYPE, 0x8808);
1357 CAS_WRITE_4(sc, CAS_MAC_RANDOM_SEED,
1363 CAS_WRITE_4(sc, i, 0);
1366 CAS_WRITE_4(sc, CAS_MAC_ADDR42, 0x0001);
1367 CAS_WRITE_4(sc, CAS_MAC_ADDR43, 0xc200);
1368 CAS_WRITE_4(sc, CAS_MAC_ADDR44, 0x0180);
1371 CAS_WRITE_4(sc, CAS_MAC_AFILTER0, 0);
1372 CAS_WRITE_4(sc, CAS_MAC_AFILTER1, 0);
1373 CAS_WRITE_4(sc, CAS_MAC_AFILTER2, 0);
1374 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK1_2, 0);
1375 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK0, 0);
1380 CAS_WRITE_4(sc, i, 0);
1386 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0);
1387 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0);
1388 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0);
1389 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0);
1390 CAS_WRITE_4(sc, CAS_MAC_DEFER_TMR_CNT, 0);
1391 CAS_WRITE_4(sc, CAS_MAC_PEAK_ATTEMPTS, 0);
1392 CAS_WRITE_4(sc, CAS_MAC_RX_FRAME_COUNT, 0);
1393 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0);
1394 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0);
1395 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0);
1396 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0);
1399 CAS_WRITE_4(sc, CAS_MAC_SPC, 0x1BF0 << CAS_MAC_SPC_TIME_SHFT);
1402 CAS_WRITE_4(sc, CAS_MAC_ADDR0, (laddr[4] << 8) | laddr[5]);
1403 CAS_WRITE_4(sc, CAS_MAC_ADDR1, (laddr[2] << 8) | laddr[3]);
1404 CAS_WRITE_4(sc, CAS_MAC_ADDR2, (laddr[0] << 8) | laddr[1]);
1407 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, CAS_MAC_XIF_CONF_TX_OE);
1434 CAS_WRITE_4(sc, CAS_TX_KICK3, sc->sc_txnext);
1859 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, sc->sc_rxcptr);
1915 CAS_WRITE_4(sc, CAS_RX_KICK,
1957 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff);
2074 CAS_WRITE_4(sc, CAS_INTMASK,
2127 CAS_WRITE_4(sc, CAS_MIF_CONF,
2191 CAS_WRITE_4(sc, CAS_MIF_FRAME, v);
2226 CAS_WRITE_4(sc, CAS_PCS_CTRL, val);
2235 CAS_WRITE_4(sc, CAS_PCS_CONF, 0);
2238 CAS_WRITE_4(sc, CAS_PCS_ANAR, val);
2241 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL,
2245 CAS_WRITE_4(sc, CAS_PCS_CONF,
2258 CAS_WRITE_4(sc, reg, val);
2270 CAS_WRITE_4(sc, CAS_MIF_FRAME, v);
2337 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, txcfg);
2339 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, rxcfg);
2349 CAS_WRITE_4(sc, CAS_MAC_CTRL_CONF, v);
2370 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x41);
2372 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7);
2377 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME,
2380 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME,
2394 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, v);
2399 CAS_WRITE_4(sc, CAS_MAC_TX_CONF,
2401 CAS_WRITE_4(sc, CAS_MAC_RX_CONF,
2530 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v);
2564 CAS_WRITE_4(sc,
2570 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v | CAS_MAC_RX_CONF_EN);
2752 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN,
2852 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, 0);