Lines Matching refs:BHND_PMU_WRITE_4
447 BHND_PMU_WRITE_4(sc, BHND_PMU_CTRL, pctrl);
1019 BHND_PMU_WRITE_4(sc, BHND_PMU_RES_TABLE_SEL, updt->resnum);
1020 BHND_PMU_WRITE_4(sc, BHND_PMU_RES_UPDN_TIMER, updt->updown);
1042 BHND_PMU_WRITE_4(sc, BHND_PMU_RES_TABLE_SEL, i);
1043 BHND_PMU_WRITE_4(sc, BHND_PMU_RES_UPDN_TIMER, val);
1064 BHND_PMU_WRITE_4(sc, BHND_PMU_RES_TABLE_SEL, i);
1117 BHND_PMU_WRITE_4(sc, BHND_PMU_RES_TABLE_SEL, i);
1118 BHND_PMU_WRITE_4(sc, BHND_PMU_RES_DEP_MASK, val);
1130 BHND_PMU_WRITE_4(sc, BHND_PMU_MAX_RES_MASK, max_mask);
1137 BHND_PMU_WRITE_4(sc, BHND_PMU_MIN_RES_MASK, min_mask);
1596 BHND_PMU_WRITE_4(sc, BHND_PMU_CTRL, pmu_ctrl);
1913 BHND_PMU_WRITE_4(sc, BHND_PMU1_PLL0_PLLCTL4, plldata);
1992 BHND_PMU_WRITE_4(sc, BHND_PMU_CTRL, pmuctrl);
2082 BHND_PMU_WRITE_4(sc, BHND_PMU_MAX_RES_MASK, max_mask);
2084 BHND_PMU_WRITE_4(sc, BHND_PMU_MIN_RES_MASK, min_mask);
2250 BHND_PMU_WRITE_4(sc, BHND_PMU_PLL_CONTROL_ADDR,
2259 BHND_PMU_WRITE_4(sc, BHND_PMU_PLL_CONTROL_ADDR,
2268 BHND_PMU_WRITE_4(sc, BHND_PMU_PLL_CONTROL_ADDR,
2293 BHND_PMU_WRITE_4(sc, BHND_PMU_PLL_CONTROL_ADDR,
2721 BHND_PMU_WRITE_4(sc, BHND_PMU_RES_TABLE_SEL, rsrc);
2770 BHND_PMU_WRITE_4(sc, BHND_PMU_RES_TABLE_SEL, i);
2879 BHND_PMU_WRITE_4(sc, BHND_PMU_CHIP_CONTROL_ADDR, 1);
2915 BHND_PMU_WRITE_4(sc, BHND_PMU_REG_CONTROL_ADDR, 0);
2919 BHND_PMU_WRITE_4(sc, BHND_PMU_REG_CONTROL_DATA, val);
2921 BHND_PMU_WRITE_4(sc, BHND_PMU_REG_CONTROL_ADDR, 1);
2925 BHND_PMU_WRITE_4(sc, BHND_PMU_REG_CONTROL_DATA, val);
2928 BHND_PMU_WRITE_4(sc, BHND_PMU_CHIP_CONTROL_ADDR, 0);
2932 BHND_PMU_WRITE_4(sc, BHND_PMU_CHIP_CONTROL_DATA, val);
2934 BHND_PMU_WRITE_4(sc, BHND_PMU_CHIP_CONTROL_ADDR, 1);
2938 BHND_PMU_WRITE_4(sc, BHND_PMU_CHIP_CONTROL_DATA, val);
2941 BHND_PMU_WRITE_4(sc, BHND_PMU_CHIP_CONTROL_ADDR, 0);
2945 BHND_PMU_WRITE_4(sc, BHND_PMU_CHIP_CONTROL_ADDR, 1);
3538 BHND_PMU_WRITE_4(sc, BHND_PMU_XTALFREQ, 1U <<
3550 BHND_PMU_WRITE_4(sc, BHND_PMU_XTALFREQ, 0);