Lines Matching refs:amn
111 struct amrr_node *amn = ATH_NODE_AMRR(an);
113 *rix = amn->amn_tx_rix0;
114 *try0 = amn->amn_tx_try0;
116 *txrate = amn->amn_tx_rate0sp;
118 *txrate = amn->amn_tx_rate0;
133 struct amrr_node *amn = ATH_NODE_AMRR(an);
137 rc[0].rix = amn->amn_tx_rate0;
138 rc[1].rix = amn->amn_tx_rate1;
139 rc[2].rix = amn->amn_tx_rate2;
140 rc[3].rix = amn->amn_tx_rate3;
142 rc[0].tries = amn->amn_tx_try0;
143 rc[1].tries = amn->amn_tx_try1;
144 rc[2].tries = amn->amn_tx_try2;
145 rc[3].tries = amn->amn_tx_try3;
152 struct amrr_node *amn = ATH_NODE_AMRR(an);
155 , amn->amn_tx_rate1sp, amn->amn_tx_try1 /* series 1 */
156 , amn->amn_tx_rate2sp, amn->amn_tx_try2 /* series 2 */
157 , amn->amn_tx_rate3sp, amn->amn_tx_try3 /* series 3 */
166 struct amrr_node *amn = ATH_NODE_AMRR(an);
171 amn->amn_tx_try0_cnt++;
173 amn->amn_tx_try1_cnt++;
175 amn->amn_tx_try1_cnt++;
176 amn->amn_tx_try2_cnt++;
178 amn->amn_tx_try1_cnt++;
179 amn->amn_tx_try2_cnt++;
180 amn->amn_tx_try3_cnt++;
182 amn->amn_tx_try1_cnt++;
183 amn->amn_tx_try2_cnt++;
184 amn->amn_tx_try3_cnt++;
185 amn->amn_tx_failure_cnt++;
187 if (amn->amn_interval != 0 &&
188 ticks - amn->amn_ticks > amn->amn_interval) {
190 amn->amn_ticks = ticks;
207 node_reset(struct amrr_node *amn)
209 amn->amn_tx_try0_cnt = 0;
210 amn->amn_tx_try1_cnt = 0;
211 amn->amn_tx_try2_cnt = 0;
212 amn->amn_tx_try3_cnt = 0;
213 amn->amn_tx_failure_cnt = 0;
214 amn->amn_success = 0;
215 amn->amn_recovery = 0;
216 amn->amn_success_threshold = ath_rate_min_success_threshold;
229 struct amrr_node *amn = ATH_NODE_AMRR(an);
241 amn->amn_rix = rate;
251 amn->amn_tx_rix0 = sc->sc_rixmap[ni->ni_txrate];
252 amn->amn_tx_rate0 = rt->info[amn->amn_tx_rix0].rateCode;
253 amn->amn_tx_rate0sp = amn->amn_tx_rate0 |
254 rt->info[amn->amn_tx_rix0].shortPreamble;
256 amn->amn_tx_try0 = 1;
257 amn->amn_tx_try1 = 1;
258 amn->amn_tx_try2 = 1;
259 amn->amn_tx_try3 = 1;
263 amn->amn_tx_rate1 = rt->info[rix].rateCode;
264 amn->amn_tx_rate1sp = amn->amn_tx_rate1 |
267 amn->amn_tx_rate1 = amn->amn_tx_rate1sp = 0;
272 amn->amn_tx_rate2 = rt->info[rix].rateCode;
273 amn->amn_tx_rate2sp = amn->amn_tx_rate2 |
276 amn->amn_tx_rate2 = amn->amn_tx_rate2sp = 0;
280 amn->amn_tx_rate3 = rt->info[0].rateCode;
281 amn->amn_tx_rate3sp =
282 amn->amn_tx_rate3 | rt->info[0].shortPreamble;
284 amn->amn_tx_rate3 = amn->amn_tx_rate3sp = 0;
287 amn->amn_tx_try0 = ATH_TXMAXTRY;
291 amn->amn_tx_try1 = 0;
292 amn->amn_tx_try2 = 0;
293 amn->amn_tx_try3 = 0;
294 amn->amn_tx_rate1 = amn->amn_tx_rate1sp = 0;
295 amn->amn_tx_rate2 = amn->amn_tx_rate2sp = 0;
296 amn->amn_tx_rate3 = amn->amn_tx_rate3sp = 0;
299 node_reset(amn);
301 amn->amn_interval = ath_rateinterval;
303 amn->amn_interval /= 2;
304 amn->amn_interval = (amn->amn_interval * hz) / 1000;
364 struct amrr_node *amn = ATH_NODE_AMRR(ATH_NODE (ni));
367 #define is_success(amn) \
368 (amn->amn_tx_try1_cnt < (amn->amn_tx_try0_cnt/10))
369 #define is_enough(amn) \
370 (amn->amn_tx_try0_cnt > 10)
371 #define is_failure(amn) \
372 (amn->amn_tx_try1_cnt > (amn->amn_tx_try0_cnt/3))
374 rix = amn->amn_rix;
378 amn->amn_tx_try0_cnt, amn->amn_tx_try1_cnt, amn->amn_tx_try2_cnt,
379 amn->amn_tx_try3_cnt, amn->amn_success_threshold);
380 if (is_success (amn) && is_enough (amn)) {
381 amn->amn_success++;
382 if (amn->amn_success == amn->amn_success_threshold &&
384 amn->amn_recovery = 1;
385 amn->amn_success = 0;
390 amn->amn_recovery = 0;
392 } else if (is_failure (amn)) {
393 amn->amn_success = 0;
395 if (amn->amn_recovery) {
397 amn->amn_success_threshold *= 2;
398 amn->amn_success_threshold = min (amn->amn_success_threshold,
403 amn->amn_success_threshold);
406 amn->amn_success_threshold = ath_rate_min_success_threshold;
410 amn->amn_success_threshold);
412 amn->amn_recovery = 0;
415 amn->amn_recovery = 0;
418 if (is_enough (amn) || rix != amn->amn_rix) {
420 amn->amn_tx_try0_cnt = 0;
421 amn->amn_tx_try1_cnt = 0;
422 amn->amn_tx_try2_cnt = 0;
423 amn->amn_tx_try3_cnt = 0;
424 amn->amn_tx_failure_cnt = 0;
426 if (rix != amn->amn_rix) {