Lines Matching refs:regVal
66 int regVal;
88 regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
89 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL));
93 regVal |= SM(ant_div_control1, AR_PHY_9285_ANT_DIV_CTL);
98 regVal |= SM(ant_div_control2, AR_PHY_9285_ANT_DIV_ALT_LNACONF);
99 regVal |= SM((ant_div_control2 >> 2), AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
100 regVal |= SM((ant_div_control1 >> 1), AR_PHY_9285_ANT_DIV_ALT_GAINTB);
101 regVal |= SM((ant_div_control1 >> 2), AR_PHY_9285_ANT_DIV_MAIN_GAINTB);
107 regVal |= SM(HAL_ANT_DIV_COMB_LNA2, AR_PHY_9285_ANT_DIV_ALT_LNACONF);
108 regVal |= SM(HAL_ANT_DIV_COMB_LNA1, AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
109 regVal |= SM(AR_PHY_9285_ANT_DIV_GAINTB_0, AR_PHY_9285_ANT_DIV_ALT_GAINTB);
110 regVal |= SM(AR_PHY_9285_ANT_DIV_GAINTB_1, AR_PHY_9285_ANT_DIV_MAIN_GAINTB);
116 regVal |= SM(HAL_ANT_DIV_COMB_LNA1, AR_PHY_9285_ANT_DIV_ALT_LNACONF);
117 regVal |= SM(HAL_ANT_DIV_COMB_LNA2, AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
118 regVal |= SM(AR_PHY_9285_ANT_DIV_GAINTB_1, AR_PHY_9285_ANT_DIV_ALT_GAINTB);
119 regVal |= SM(AR_PHY_9285_ANT_DIV_GAINTB_0, AR_PHY_9285_ANT_DIV_MAIN_GAINTB);
123 OS_REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);
124 regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
125 regVal = OS_REG_READ(ah, AR_PHY_CCK_DETECT);
126 regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
128 regVal |= SM((ant_div_control1 >> 3), AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
130 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal);
131 regVal = OS_REG_READ(ah, AR_PHY_CCK_DETECT);
148 regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
149 regVal &= (~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF | AR_PHY_9285_ANT_DIV_ALT_LNACONF));
150 regVal |= (HAL_ANT_DIV_COMB_LNA1 << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S);
151 regVal |= (HAL_ANT_DIV_COMB_LNA2 << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S);
152 regVal &= (~(AR_PHY_9285_FAST_DIV_BIAS));
153 regVal |= (0 << AR_PHY_9285_FAST_DIV_BIAS_S);
154 OS_REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);