Lines Matching refs:desc
299 softdma_process_tx(struct softdma_channel *chan, struct softdma_desc *desc)
315 if (desc->control & CONTROL_GEN_SOP)
322 addr = desc->src_addr;
323 len = desc->len;
347 (desc->control & CONTROL_GEN_EOP) != 0)
373 (desc->control & CONTROL_GEN_EOP) != 0)
391 return (desc->len);
395 softdma_process_rx(struct softdma_channel *chan, struct softdma_desc *desc)
419 len = desc->len;
452 *(uint32_t *)(desc->dst_addr + dst_offs) = data;
455 *(uint16_t *)(desc->dst_addr + dst_offs) =
459 *(uint8_t *)(desc->dst_addr + dst_offs) =
492 struct softdma_desc *desc;
501 desc = &chan->descs[chan->idx_tail];
503 while (desc != NULL) {
504 if ((desc->control & CONTROL_OWN) == 0) {
508 if (desc->direction == XDMA_MEM_TO_DEV) {
509 ret = softdma_process_tx(chan, desc);
511 ret = softdma_process_rx(chan, desc);
519 desc->control = 0;
542 desc = desc->next;
678 struct softdma_desc *desc;
695 desc = &chan->descs[i];
698 desc->next = &chan->descs[0];
700 desc->next = &chan->descs[i+1];
729 struct softdma_desc *desc;
746 desc = &chan->descs[chan->idx_head];
747 desc->src_addr = sg[i].src_addr;
748 desc->dst_addr = sg[i].dst_addr;
750 desc->src_incr = 1;
751 desc->dst_incr = 0;
753 desc->src_incr = 0;
754 desc->dst_incr = 1;
756 desc->direction = sg[i].direction;
758 desc->len = len;
759 desc->transfered = 0;
760 desc->status = 0;
761 desc->reserved = 0;
762 desc->control = 0;
765 desc->control |= CONTROL_GEN_SOP;
767 desc->control |= CONTROL_GEN_EOP;
772 desc->control |= CONTROL_OWN;
795 struct softdma_desc *desc;
810 desc = &chan->descs[0];
812 desc->src_addr = req->src_addr;
813 desc->dst_addr = req->dst_addr;
814 desc->len = req->block_len;
815 desc->src_incr = 1;
816 desc->dst_incr = 1;
817 desc->next = NULL;