Lines Matching defs:val4
127 csr_write_4(struct atse_softc *sc, uint32_t reg, uint32_t val4,
131 val4 = htole32(val4);
133 "atse_mem_res", reg, reg * 4, val4);
134 bus_write_4(sc->atse_mem_res, reg * 4, val4);
140 uint32_t val4;
142 val4 = le32toh(bus_read_4(sc->atse_mem_res, reg * 4));
144 "atse_mem_res", reg, reg * 4, val4);
146 return (val4);
157 uint32_t val4;
159 val4 = htole32(val & 0x0000ffff);
161 "atse_mem_res", reg, (bmcr + reg) * 4, val4);
162 bus_write_4(sc->atse_mem_res, (bmcr + reg) * 4, val4);
169 uint32_t val4;
172 val4 = bus_read_4(sc->atse_mem_res, (bmcr + reg) * 4);
173 val = le32toh(val4) & 0x0000ffff;
394 uint32_t mask, val4;
407 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
408 val4 &= ~mask;
409 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4);
413 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
414 if ((val4 & mask) == 0) {
420 if ((val4 & mask) != 0) {
454 uint32_t val4;
458 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
460 if ((val4 & BASE_CFG_COMMAND_CONFIG_MHASH_SEL) != 0)
461 val4 &= ~BASE_CFG_COMMAND_CONFIG_MHASH_SEL;
465 val4 |= BASE_CFG_COMMAND_CONFIG_PROMIS_EN;
467 val4 &= ~BASE_CFG_COMMAND_CONFIG_PROMIS_EN;
470 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4);
551 uint32_t val4;
568 val4 = atse_ethernet_option_bits[0] << 24;
569 val4 |= atse_ethernet_option_bits[1] << 16;
570 val4 |= atse_ethernet_option_bits[2] << 8;
571 val4 |= atse_ethernet_option_bits[3];
573 if (val4 != le32toh(0x00005afe)) {
576 val4);
699 uint32_t val4, mask;
748 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
749 val4 &= ~mask;
751 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4);
754 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
755 if ((val4 & mask) == 0) {
760 if ((val4 & mask) != 0) {
790 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
799 val4 |= BASE_CFG_COMMAND_CONFIG_ETH_SPEED;
801 val4 &= ~BASE_CFG_COMMAND_CONFIG_ETH_SPEED;
803 val4 &= ~BASE_CFG_COMMAND_CONFIG_ENA_10;
810 val4 |= BASE_CFG_COMMAND_CONFIG_TX_ADDR_INS;
812 val4 |= BASE_CFG_COMMAND_CONFIG_PAD_EN;
813 val4 &= ~BASE_CFG_COMMAND_CONFIG_CRC_FWD;
815 val4 |= BASE_CFG_COMMAND_CONFIG_CNTL_FRM_ENA;
818 val4 |= BASE_CFG_COMMAND_CONFIG_RX_ERR_DISC;
821 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4);
828 val4 = CSR_READ_4(sc, TX_CMD_STAT);
829 val4 &= ~(TX_CMD_STAT_OMIT_CRC|TX_CMD_STAT_TX_SHIFT16);
830 CSR_WRITE_4(sc, TX_CMD_STAT, val4);
832 val4 = CSR_READ_4(sc, RX_CMD_STAT);
833 val4 &= ~RX_CMD_STAT_RX_SHIFT16;
834 val4 |= RX_CMD_STAT_RX_SHIFT16;
835 CSR_WRITE_4(sc, RX_CMD_STAT, val4);
838 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
839 val4 |= BASE_CFG_COMMAND_CONFIG_SW_RESET;
840 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4);
843 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
844 if ((val4 & BASE_CFG_COMMAND_CONFIG_SW_RESET) == 0) {
849 if ((val4 & BASE_CFG_COMMAND_CONFIG_SW_RESET) != 0) {
856 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
857 val4 |= mask;
858 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4);
861 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
862 if ((val4 & mask) == mask) {
867 if ((val4 & mask) != mask) {
1541 uint32_t val4;
1553 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
1562 val4 |= BASE_CFG_COMMAND_CONFIG_ENA_10;
1563 val4 &= ~BASE_CFG_COMMAND_CONFIG_ETH_SPEED;
1567 val4 &= ~BASE_CFG_COMMAND_CONFIG_ENA_10;
1568 val4 &= ~BASE_CFG_COMMAND_CONFIG_ETH_SPEED;
1572 val4 &= ~BASE_CFG_COMMAND_CONFIG_ENA_10;
1573 val4 |= BASE_CFG_COMMAND_CONFIG_ETH_SPEED;
1587 val4 &= ~BASE_CFG_COMMAND_CONFIG_HD_ENA;
1589 val4 |= BASE_CFG_COMMAND_CONFIG_HD_ENA;
1595 val4 |= BASE_CFG_COMMAND_CONFIG_TX_ENA;
1596 val4 |= BASE_CFG_COMMAND_CONFIG_RX_ENA;
1598 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4);