Lines Matching refs:spi
705 cpi->xport_specific.spi.ppr_options = SID_SPI_CLOCK_DT_ST
725 struct ccb_trans_settings_spi *spi;
733 spi = &cts->xport_specific.spi;
762 if ((spi->valid & CTS_SPI_VALID_DISC) != 0) {
763 if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB) != 0)
776 if ((spi->valid & CTS_SPI_VALID_BUS_WIDTH) != 0) {
778 &spi->bus_width, ROLE_UNKNOWN);
779 ahd_set_width(ahd, &devinfo, spi->bus_width,
783 if ((spi->valid & CTS_SPI_VALID_PPR_OPTIONS) == 0) {
785 spi->ppr_options = tinfo->user.ppr_options;
787 spi->ppr_options = tinfo->goal.ppr_options;
790 if ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) == 0) {
792 spi->sync_offset = tinfo->user.offset;
794 spi->sync_offset = tinfo->goal.offset;
797 if ((spi->valid & CTS_SPI_VALID_SYNC_RATE) == 0) {
799 spi->sync_period = tinfo->user.period;
801 spi->sync_period = tinfo->goal.period;
804 if (((spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0)
805 || ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) != 0)) {
810 if (spi->bus_width != MSG_EXT_WDTR_BUS_16_BIT)
811 spi->ppr_options &= ~MSG_EXT_PPR_DT_REQ;
814 spi->ppr_options &= ~MSG_EXT_PPR_IU_REQ;
816 ahd_find_syncrate(ahd, &spi->sync_period,
817 &spi->ppr_options, maxsync);
819 spi->sync_period, &spi->sync_offset,
820 spi->bus_width, ROLE_UNKNOWN);
823 if (spi->sync_offset == 0) {
824 spi->sync_period = 0;
825 spi->ppr_options = 0;
828 ahd_set_syncrate(ahd, &devinfo, spi->sync_period,
829 spi->sync_offset, spi->ppr_options,
841 struct ccb_trans_settings_spi *spi;
847 spi = &cts->xport_specific.spi;
862 spi->flags &= ~CTS_SPI_FLAGS_DISC_ENB;
865 spi->flags |= CTS_SPI_FLAGS_DISC_ENB;
871 spi->flags |= CTS_SPI_FLAGS_DISC_ENB;
879 spi->sync_period = tinfo->period;
880 spi->sync_offset = tinfo->offset;
881 spi->bus_width = tinfo->width;
882 spi->ppr_options = tinfo->ppr_options;
886 spi->valid = CTS_SPI_VALID_SYNC_RATE
893 spi->valid |= CTS_SPI_VALID_DISC;