Lines Matching refs:v1
1113 ld1 {v0.2d,v1.2d,v2.2d,v3.2d},[x0] // load context
1132 orr v27.16b,v1.16b,v1.16b
1140 ext v6.16b,v1.16b,v2.16b,#8
1146 add v4.2d,v1.2d,v3.2d // "D + T1"
1147 .inst 0xce608423 //sha512h2 v3.16b,v1.16b,v0.16b
1158 add v1.2d,v0.2d,v2.2d // "D + T1"
1163 ext v5.16b,v1.16b,v4.16b,#8
1164 ext v6.16b,v3.16b,v1.16b,#8
1175 ext v5.16b,v0.16b,v1.16b,#8
1177 add v1.2d,v1.2d,v25.2d // "T1 + H + K512[i]"
1180 .inst 0xce6680a1 //sha512h v1.16b,v5.16b,v6.16b
1182 add v3.2d,v2.2d,v1.2d // "D + T1"
1183 .inst 0xce648441 //sha512h2 v1.16b,v2.16b,v4.16b
1195 .inst 0xce618480 //sha512h2 v0.16b,v4.16b,v1.16b
1200 ext v6.16b,v1.16b,v2.16b,#8
1206 add v4.2d,v1.2d,v3.2d // "D + T1"
1207 .inst 0xce608423 //sha512h2 v3.16b,v1.16b,v0.16b
1218 add v1.2d,v0.2d,v2.2d // "D + T1"
1223 ext v5.16b,v1.16b,v4.16b,#8
1224 ext v6.16b,v3.16b,v1.16b,#8
1235 ext v5.16b,v0.16b,v1.16b,#8
1237 add v1.2d,v1.2d,v24.2d // "T1 + H + K512[i]"
1240 .inst 0xce6680a1 //sha512h v1.16b,v5.16b,v6.16b
1242 add v3.2d,v2.2d,v1.2d // "D + T1"
1243 .inst 0xce648441 //sha512h2 v1.16b,v2.16b,v4.16b
1255 .inst 0xce618480 //sha512h2 v0.16b,v4.16b,v1.16b
1260 ext v6.16b,v1.16b,v2.16b,#8
1266 add v4.2d,v1.2d,v3.2d // "D + T1"
1267 .inst 0xce608423 //sha512h2 v3.16b,v1.16b,v0.16b
1278 add v1.2d,v0.2d,v2.2d // "D + T1"
1283 ext v5.16b,v1.16b,v4.16b,#8
1284 ext v6.16b,v3.16b,v1.16b,#8
1295 ext v5.16b,v0.16b,v1.16b,#8
1297 add v1.2d,v1.2d,v25.2d // "T1 + H + K512[i]"
1300 .inst 0xce6680a1 //sha512h v1.16b,v5.16b,v6.16b
1302 add v3.2d,v2.2d,v1.2d // "D + T1"
1303 .inst 0xce648441 //sha512h2 v1.16b,v2.16b,v4.16b
1315 .inst 0xce618480 //sha512h2 v0.16b,v4.16b,v1.16b
1320 ext v6.16b,v1.16b,v2.16b,#8
1326 add v4.2d,v1.2d,v3.2d // "D + T1"
1327 .inst 0xce608423 //sha512h2 v3.16b,v1.16b,v0.16b
1338 add v1.2d,v0.2d,v2.2d // "D + T1"
1343 ext v5.16b,v1.16b,v4.16b,#8
1344 ext v6.16b,v3.16b,v1.16b,#8
1355 ext v5.16b,v0.16b,v1.16b,#8
1357 add v1.2d,v1.2d,v24.2d // "T1 + H + K512[i]"
1360 .inst 0xce6680a1 //sha512h v1.16b,v5.16b,v6.16b
1362 add v3.2d,v2.2d,v1.2d // "D + T1"
1363 .inst 0xce648441 //sha512h2 v1.16b,v2.16b,v4.16b
1375 .inst 0xce618480 //sha512h2 v0.16b,v4.16b,v1.16b
1380 ext v6.16b,v1.16b,v2.16b,#8
1386 add v4.2d,v1.2d,v3.2d // "D + T1"
1387 .inst 0xce608423 //sha512h2 v3.16b,v1.16b,v0.16b
1398 add v1.2d,v0.2d,v2.2d // "D + T1"
1403 ext v5.16b,v1.16b,v4.16b,#8
1404 ext v6.16b,v3.16b,v1.16b,#8
1415 ext v5.16b,v0.16b,v1.16b,#8
1417 add v1.2d,v1.2d,v25.2d // "T1 + H + K512[i]"
1420 .inst 0xce6680a1 //sha512h v1.16b,v5.16b,v6.16b
1422 add v3.2d,v2.2d,v1.2d // "D + T1"
1423 .inst 0xce648441 //sha512h2 v1.16b,v2.16b,v4.16b
1435 .inst 0xce618480 //sha512h2 v0.16b,v4.16b,v1.16b
1440 ext v6.16b,v1.16b,v2.16b,#8
1446 add v4.2d,v1.2d,v3.2d // "D + T1"
1447 .inst 0xce608423 //sha512h2 v3.16b,v1.16b,v0.16b
1458 add v1.2d,v0.2d,v2.2d // "D + T1"
1463 ext v5.16b,v1.16b,v4.16b,#8
1464 ext v6.16b,v3.16b,v1.16b,#8
1475 ext v5.16b,v0.16b,v1.16b,#8
1477 add v1.2d,v1.2d,v24.2d // "T1 + H + K512[i]"
1480 .inst 0xce6680a1 //sha512h v1.16b,v5.16b,v6.16b
1482 add v3.2d,v2.2d,v1.2d // "D + T1"
1483 .inst 0xce648441 //sha512h2 v1.16b,v2.16b,v4.16b
1495 .inst 0xce618480 //sha512h2 v0.16b,v4.16b,v1.16b
1500 ext v6.16b,v1.16b,v2.16b,#8
1506 add v4.2d,v1.2d,v3.2d // "D + T1"
1507 .inst 0xce608423 //sha512h2 v3.16b,v1.16b,v0.16b
1518 add v1.2d,v0.2d,v2.2d // "D + T1"
1524 ext v5.16b,v1.16b,v4.16b,#8
1525 ext v6.16b,v3.16b,v1.16b,#8
1535 ext v5.16b,v0.16b,v1.16b,#8
1537 add v1.2d,v1.2d,v25.2d // "T1 + H + K512[i]"
1538 .inst 0xce6680a1 //sha512h v1.16b,v5.16b,v6.16b
1540 add v3.2d,v2.2d,v1.2d // "D + T1"
1541 .inst 0xce648441 //sha512h2 v1.16b,v2.16b,v4.16b
1552 .inst 0xce618480 //sha512h2 v0.16b,v4.16b,v1.16b
1558 ext v6.16b,v1.16b,v2.16b,#8
1562 add v4.2d,v1.2d,v3.2d // "D + T1"
1563 .inst 0xce608423 //sha512h2 v3.16b,v1.16b,v0.16b
1573 add v1.2d,v0.2d,v2.2d // "D + T1"
1579 ext v5.16b,v1.16b,v4.16b,#8
1580 ext v6.16b,v3.16b,v1.16b,#8
1590 ext v5.16b,v0.16b,v1.16b,#8
1592 add v1.2d,v1.2d,v24.2d // "T1 + H + K512[i]"
1593 .inst 0xce6680a1 //sha512h v1.16b,v5.16b,v6.16b
1595 add v3.2d,v2.2d,v1.2d // "D + T1"
1596 .inst 0xce648441 //sha512h2 v1.16b,v2.16b,v4.16b
1607 .inst 0xce618480 //sha512h2 v0.16b,v4.16b,v1.16b
1609 add v1.2d,v1.2d,v27.2d
1615 st1 {v0.2d,v1.2d,v2.2d,v3.2d},[x0] // store context