Lines Matching refs:ULL
197 #define ULL unsigned long long
720 uint64_t nand_size_bits = (64*1024*1024ULL) << ((nand_id_buffer[4] & 0x70) >> 4); /* Plane size */
732 cvmx_nand_state[chip].blocks = nand_size_bits/(8ULL*cvmx_nand_state[chip].page_size*cvmx_nand_state[chip].pages_per_block);
894 CVMX_NAND_LOG_PARAM("0x%llx", (ULL)cmd.u64[0]);
895 CVMX_NAND_LOG_PARAM("0x%llx", (ULL)cmd.u64[1]);
1166 CVMX_NAND_LOG_PARAM("0x%llx", (ULL)buffer_address);
1240 CVMX_NAND_LOG_PARAM("0x%llx", (ULL)nand_address);
1242 CVMX_NAND_LOG_PARAM("0x%llx", (ULL)buffer_address);
1332 CVMX_NAND_LOG_PARAM("0x%llx", (ULL)nand_address);
1333 CVMX_NAND_LOG_PARAM("0x%llx", (ULL)buffer_address);
1380 CVMX_NAND_LOG_PARAM("0x%llx", (ULL)nand_address);
1381 CVMX_NAND_LOG_PARAM("0x%llx", (ULL)buffer_address);
1464 CVMX_NAND_LOG_PARAM("0x%llx", (ULL)nand_address);
1532 CVMX_NAND_LOG_PARAM("0x%llx", (ULL)nand_address);
1533 CVMX_NAND_LOG_PARAM("0x%llx", (ULL)buffer_address);
1573 CVMX_NAND_LOG_PARAM("0x%llx", (ULL)buffer_address);