Lines Matching refs:ALT3
17 #define ALT3 0x3
36 #define VF610_PAD_PTA9__RMII_CLKIN 0x008 0x2F0 ALT3 0x1
57 #define VF610_PAD_PTA16__ADC1_SE0 0x018 0x000 ALT3 0x0
65 #define VF610_PAD_PTA17__ADC1_SE1 0x01C 0x000 ALT3 0x0
73 #define VF610_PAD_PTA18__FTM1_QD_PHA 0x020 0x334 ALT3 0x0
81 #define VF610_PAD_PTA19__FTM1_QD_PHB 0x024 0x338 ALT3 0x0
130 #define VF610_PAD_PTA28__ENET1_1588_TMR0 0x048 0x000 ALT3 0x0
137 #define VF610_PAD_PTA29__ENET1_1588_TMR1 0x04C 0x000 ALT3 0x0
144 #define VF610_PAD_PTA30__ENET1_1588_TMR2 0x050 0x000 ALT3 0x0
151 #define VF610_PAD_PTA31__ENET1_1588_TMR3 0x054 0x000 ALT3 0x0
158 #define VF610_PAD_PTB0__TRACE_CTL 0x058 0x000 ALT3 0x0
166 #define VF610_PAD_PTB1__SRC_RCON30 0x05C 0x000 ALT3 0x0
174 #define VF610_PAD_PTB2__SRC_RCON31 0x060 0x000 ALT3 0x0
182 #define VF610_PAD_PTB3__PDB_EXTRIG 0x064 0x000 ALT3 0x0
189 #define VF610_PAD_PTB4__ADC0_SE4 0x068 0x000 ALT3 0x0
197 #define VF610_PAD_PTB5__ADC1_SE4 0x06C 0x000 ALT3 0x0
204 #define VF610_PAD_PTB6__QSPI0_QPCS1_A 0x070 0x000 ALT3 0x0
212 #define VF610_PAD_PTB7__QSPI0_B_QPCS1 0x074 0x000 ALT3 0x0
218 #define VF610_PAD_PTB8__FTM1_QD_PHA 0x078 0x334 ALT3 0x1
223 #define VF610_PAD_PTB9__FTM1_QD_PHB 0x07C 0x338 ALT3 0x1
239 #define VF610_PAD_PTB12__DSPI0_CS5 0x088 0x000 ALT3 0x0
246 #define VF610_PAD_PTB13__DSPI0_CS4 0x08C 0x000 ALT3 0x0
291 #define VF610_PAD_PTC0__DSPI0_CS3 0x0B4 0x000 ALT3 0x0
299 #define VF610_PAD_PTC1__DSPI0_CS2 0x0B8 0x000 ALT3 0x0
321 #define VF610_PAD_PTC4__DSPI1_CS1 0x0C4 0x000 ALT3 0x0
329 #define VF610_PAD_PTC5__DSPI1_CS0 0x0C8 0x300 ALT3 0x0
336 #define VF610_PAD_PTC6__DSPI1_SIN 0x0CC 0x2FC ALT3 0x0
343 #define VF610_PAD_PTC7__DSPI1_SOUT 0x0D0 0x000 ALT3 0x0
349 #define VF610_PAD_PTC8__DSPI1_SCK 0x0D4 0x2F8 ALT3 0x0
354 #define VF610_PAD_PTC9__ESAI_SCKT 0x0D8 0x310 ALT3 0x1
359 #define VF610_PAD_PTC10__ESAI_FST 0x0DC 0x30C ALT3 0x1
364 #define VF610_PAD_PTC11__ESAI_SDO0 0x0E0 0x314 ALT3 0x1
369 #define VF610_PAD_PTC12__ESAI_SDO1 0x0E4 0x318 ALT3 0x1
374 #define VF610_PAD_PTC13__ESAI_SDO2 0x0E8 0x31C ALT3 0x1
379 #define VF610_PAD_PTC14__ESAI_SDO3 0x0EC 0x320 ALT3 0x1
386 #define VF610_PAD_PTC15__ESAI_SDI0 0x0F0 0x328 ALT3 0x1
393 #define VF610_PAD_PTC16__ESAI_SDI1 0x0F4 0x324 ALT3 0x1
400 #define VF610_PAD_PTC17__ADC1_SE7 0x0F8 0x000 ALT3 0x0
426 #define VF610_PAD_PTD28__I2C2_SCL 0x108 0x34C ALT3 0x1
433 #define VF610_PAD_PTD27__I2C2_SDA 0x10C 0x350 ALT3 0x1
456 #define VF610_PAD_PTD23__FTM2_CH0 0x11C 0x000 ALT3 0x0
464 #define VF610_PAD_PTD22__FTM2_CH1 0x120 0x000 ALT3 0x0
486 #define VF610_PAD_PTD19__ESAI_SCKR 0x12C 0x000 ALT3 0x0
493 #define VF610_PAD_PTD18__ESAI_FSR 0x130 0x000 ALT3 0x0
500 #define VF610_PAD_PTD17__ESAI_HCKR 0x134 0x000 ALT3 0x0
506 #define VF610_PAD_PTD16__ESAI_HCKT 0x138 0x000 ALT3 0x0
524 #define VF610_PAD_PTD2__DSPI1_CS3 0x144 0x000 ALT3 0x0
531 #define VF610_PAD_PTD3__DSPI1_CS2 0x148 0x000 ALT3 0x0
537 #define VF610_PAD_PTD4__DSPI1_CS1 0x14C 0x000 ALT3 0x0
543 #define VF610_PAD_PTD5__DSPI1_CS0 0x150 0x300 ALT3 0x1
548 #define VF610_PAD_PTD6__DSPI1_SIN 0x154 0x2FC ALT3 0x1
553 #define VF610_PAD_PTD7__DSPI1_SOUT 0x158 0x000 ALT3 0x0
559 #define VF610_PAD_PTD8__DSPI1_SCK 0x15C 0x2F8 ALT3 0x1
591 #define VF610_PAD_PTB23__SRC_RCON18 0x174 0x398 ALT3 0x1
599 #define VF610_PAD_PTB24__SRC_RCON19 0x178 0x39C ALT3 0x1
607 #define VF610_PAD_PTB25__SRC_RCON20 0x17C 0x3A0 ALT3 0x1
614 #define VF610_PAD_PTB26__SRC_RCON21 0x180 0x000 ALT3 0x0
620 #define VF610_PAD_PTB27__SRC_RCON22 0x184 0x000 ALT3 0x0
627 #define VF610_PAD_PTB28__SRC_RCON23 0x188 0x000 ALT3 0x0
633 #define VF610_PAD_PTC26__SRC_RCON24 0x18C 0x000 ALT3 0x0
640 #define VF610_PAD_PTC27__SRC_RCON25 0x190 0x000 ALT3 0x0
648 #define VF610_PAD_PTC28__SRC_RCON26 0x194 0x000 ALT3 0x0
656 #define VF610_PAD_PTC29__SRC_RCON27 0x198 0x000 ALT3 0x0
663 #define VF610_PAD_PTC30__SRC_RCON28 0x19C 0x000 ALT3 0x0
670 #define VF610_PAD_PTC31__SRC_RCON29 0x1A0 0x000 ALT3 0x0
705 #define VF610_PAD_PTE7__SRC_RCON0 0x1C0 0x000 ALT3 0x0
710 #define VF610_PAD_PTE8__SRC_RCON1 0x1C4 0x000 ALT3 0x0
715 #define VF610_PAD_PTE9__SRC_RCON2 0x1C8 0x000 ALT3 0x0
720 #define VF610_PAD_PTE10__SRC_RCON3 0x1CC 0x000 ALT3 0x0
725 #define VF610_PAD_PTE11__SRC_RCON4 0x1D0 0x000 ALT3 0x0
731 #define VF610_PAD_PTE12__SRC_RCON5 0x1D4 0x000 ALT3 0x0
744 #define VF610_PAD_PTE15__SRC_RCON6 0x1E0 0x000 ALT3 0x0
749 #define VF610_PAD_PTE16__SRC_RCON7 0x1E4 0x000 ALT3 0x0
753 #define VF610_PAD_PTE17__SRC_RCON8 0x1E8 0x000 ALT3 0x0
757 #define VF610_PAD_PTE18__SRC_RCON9 0x1EC 0x000 ALT3 0x0
761 #define VF610_PAD_PTE19__SRC_RCON10 0x1F0 0x000 ALT3 0x0
766 #define VF610_PAD_PTE20__SRC_RCON11 0x1F4 0x000 ALT3 0x0
778 #define VF610_PAD_PTE23__SRC_RCON12 0x200 0x000 ALT3 0x0
782 #define VF610_PAD_PTE24__SRC_RCON13 0x204 0x000 ALT3 0x0
786 #define VF610_PAD_PTE25__SRC_RCON14 0x208 0x000 ALT3 0x0
790 #define VF610_PAD_PTE26__SRC_RCON15 0x20C 0x000 ALT3 0x0
794 #define VF610_PAD_PTE27__SRC_RCON16 0x210 0x000 ALT3 0x0
799 #define VF610_PAD_PTE28__SRC_RCON17 0x214 0x000 ALT3 0x0