Lines Matching refs:DRA7_CLKCTRL_INDEX
9 #define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET)
14 #define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
33 #define DRA7_VIP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
34 #define DRA7_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
35 #define DRA7_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
43 #define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
44 #define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
47 #define DRA7_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
48 #define DRA7_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
49 #define DRA7_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
50 #define DRA7_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
51 #define DRA7_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
52 #define DRA7_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
53 #define DRA7_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
56 #define DRA7_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
59 #define DRA7_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
67 #define DRA7_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
68 #define DRA7_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
69 #define DRA7_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
70 #define DRA7_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
71 #define DRA7_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
72 #define DRA7_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58)
73 #define DRA7_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60)
74 #define DRA7_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68)
75 #define DRA7_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
76 #define DRA7_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
77 #define DRA7_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
78 #define DRA7_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
79 #define DRA7_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
80 #define DRA7_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98)
81 #define DRA7_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
84 #define DRA7_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
85 #define DRA7_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
88 #define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
89 #define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
92 #define DRA7_GPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
95 #define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
96 #define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
97 #define DRA7_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
98 #define DRA7_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
99 #define DRA7_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
100 #define DRA7_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
101 #define DRA7_PCIE1_CLKCTRL DRA7_CLKCTRL_INDEX(0xb0)
102 #define DRA7_PCIE2_CLKCTRL DRA7_CLKCTRL_INDEX(0xb8)
103 #define DRA7_GMAC_CLKCTRL DRA7_CLKCTRL_INDEX(0xd0)
104 #define DRA7_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0)
105 #define DRA7_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8)
106 #define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0)
170 #define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
171 #define DRA7_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
172 #define DRA7_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
173 #define DRA7_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
174 #define DRA7_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
175 #define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
176 #define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
177 #define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
178 #define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
183 #define DRA7_MPU_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
186 #define DRA7_DSP1_MMU0_DSP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
189 #define DRA7_IPU1_MMU_IPU1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
203 #define DRA7_DSP2_MMU0_DSP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
206 #define DRA7_RTC_RTCSS_CLKCTRL DRA7_CLKCTRL_INDEX(0x44)
209 #define DRA7_CAM_VIP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
210 #define DRA7_CAM_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
211 #define DRA7_CAM_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
219 #define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
220 #define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
223 #define DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
224 #define DRA7_L3MAIN1_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
225 #define DRA7_L3MAIN1_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
226 #define DRA7_L3MAIN1_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
227 #define DRA7_L3MAIN1_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
228 #define DRA7_L3MAIN1_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
229 #define DRA7_L3MAIN1_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
232 #define DRA7_IPU2_MMU_IPU2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
235 #define DRA7_DMA_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
238 #define DRA7_EMIF_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
246 #define DRA7_L4CFG_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
247 #define DRA7_L4CFG_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
248 #define DRA7_L4CFG_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
249 #define DRA7_L4CFG_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
250 #define DRA7_L4CFG_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
251 #define DRA7_L4CFG_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58)
252 #define DRA7_L4CFG_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60)
253 #define DRA7_L4CFG_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68)
254 #define DRA7_L4CFG_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
255 #define DRA7_L4CFG_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
256 #define DRA7_L4CFG_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
257 #define DRA7_L4CFG_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
258 #define DRA7_L4CFG_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
259 #define DRA7_L4CFG_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98)
260 #define DRA7_L4CFG_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
263 #define DRA7_L3INSTR_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
264 #define DRA7_L3INSTR_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
267 #define DRA7_DSS_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
268 #define DRA7_DSS_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
271 #define DRA7_L3INIT_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
272 #define DRA7_L3INIT_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
273 #define DRA7_L3INIT_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
274 #define DRA7_L3INIT_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
275 #define DRA7_L3INIT_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
276 #define DRA7_L3INIT_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
277 #define DRA7_L3INIT_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0)
278 #define DRA7_L3INIT_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8)
279 #define DRA7_L3INIT_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0)
368 #define DRA7_WKUPAON_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
369 #define DRA7_WKUPAON_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
370 #define DRA7_WKUPAON_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
371 #define DRA7_WKUPAON_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
372 #define DRA7_WKUPAON_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
373 #define DRA7_WKUPAON_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
374 #define DRA7_WKUPAON_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
375 #define DRA7_WKUPAON_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
376 #define DRA7_WKUPAON_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)