Lines Matching refs:AR9340_HOSTIF_OFFSET
4220 AR9340_HOSTIF_OFFSET(HOST_INTF_RESET_CONTROL);
4222 AR9340_HOSTIF_OFFSET(HOST_INTF_WORK_AROUND);
4224 AR9340_HOSTIF_OFFSET(HOST_INTF_PM_CTRL);
4226 AR9340_HOSTIF_OFFSET(HOST_INTF_TIMEOUT);
4228 AR9340_HOSTIF_OFFSET(HOST_INTF_SREV);
4230 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE);
4232 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE);
4234 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_ENABLE);
4236 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_MASK);
4238 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_MASK);
4240 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE);
4242 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE);
4244 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_ENABLE);
4246 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUT);
4248 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_IN);
4250 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OE);
4252 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OE1);
4254 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INTR_POLAR);
4256 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_VALUE);
4258 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX1);
4260 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX2);
4262 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX1);
4264 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX2);
4266 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX3);
4268 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_STATE);
4270 AR9340_HOSTIF_OFFSET(HOST_INTF_CLKRUN);
4272 AR9340_HOSTIF_OFFSET(HOST_INTF_EEPROM_STS);
4274 AR9340_HOSTIF_OFFSET(HOST_INTF_OBS_CTRL);
4276 AR9340_HOSTIF_OFFSET(HOST_INTF_RFSILENT);
4278 AR9340_HOSTIF_OFFSET(HOST_INTF_MISC);
4280 AR9340_HOSTIF_OFFSET(HOST_INTF_PCIE_MSI);
4282 AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TDMA_CCA_CNTL);
4284 AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TXAPSYNC);
4286 AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR);
4288 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_CAUSE);
4290 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_ENABLE);
4292 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_MASK);
4294 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_MASK);
4296 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE);
4298 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE);