Lines Matching refs:udma
71 static void al_udma_set_defaults(struct al_udma *udma)
73 uint8_t rev_id = udma->rev_id;
75 if (udma->type == UDMA_TX) {
77 (struct unit_regs*)udma->udma_regs;
93 if (udma->type == UDMA_RX) {
95 &udma->udma_regs->s2m.s2m_comp.cfg_application_ack, 0);
103 * @param udma_q udma queue data structure
112 if (udma_q->udma->type == UDMA_TX) {
126 * @param udma_q udma queue data structure
135 if (udma_q->udma->type == UDMA_TX)
155 if (udma_q->udma->type == UDMA_RX) {
157 &udma_q->udma->udma_regs->s2m.s2m_comp.cfg_1c);
162 al_reg_write32(&udma_q->udma->udma_regs->s2m.s2m_comp.cfg_1c
171 * @param udma_q udma queue data structure
204 * enable/disable udma queue
206 * @param udma_q udma queue data structure
231 * Initialize the udma engine
233 int al_udma_init(struct al_udma *udma, struct al_udma_params *udma_params)
237 al_assert(udma);
240 al_err("udma: invalid num_of_queues parameter\n");
244 udma->type = udma_params->type;
245 udma->num_of_queues = udma_params->num_of_queues;
246 udma->gen_regs = &udma_params->udma_regs_base->gen;
248 if (udma->type == UDMA_TX)
249 udma->udma_regs = (union udma_regs *)&udma_params->udma_regs_base->m2s;
251 udma->udma_regs = (union udma_regs *)&udma_params->udma_regs_base->s2m;
253 udma->rev_id = al_udma_get_revision(udma_params->udma_regs_base);
256 udma->name = "";
258 udma->name = udma_params->name;
260 udma->state = UDMA_DISABLE;
262 udma->udma_q[i].status = AL_QUEUE_NOT_INITIALIZED;
265 al_udma_set_defaults(udma);
266 al_dbg("udma [%s] initialized. base %p\n", udma->name,
267 udma->udma_regs);
272 * Initialize the udma queue data structure
274 int al_udma_q_init(struct al_udma *udma, uint32_t qid,
279 al_assert(udma);
282 if (qid >= udma->num_of_queues) {
283 al_err("udma: invalid queue id (%d)\n", qid);
287 if (udma->udma_q[qid].status == AL_QUEUE_ENABLED) {
288 al_err("udma: queue (%d) already enabled!\n", qid);
293 al_err("udma: queue (%d) size too small\n", qid);
298 al_err("udma: queue (%d) size too large\n", qid);
303 al_err("udma: queue (%d) size (%d) must be power of 2\n",
308 udma_q = &udma->udma_q[qid];
310 if (udma->type == UDMA_TX)
312 &udma->udma_regs->m2s.m2s_q[qid];
315 &udma->udma_regs->s2m.s2m_q[qid];
341 udma_q->udma = udma;
352 al_dbg("udma [%s %d]: %s q init. size 0x%x\n"
354 udma_q->udma->name, udma_q->qid,
355 udma->type == UDMA_TX ? "Tx" : "Rx",
368 * Reset a udma queue
398 al_err("udma [%s %d]: %s timeout waiting for prefetch and "
399 "scheduler disable\n", udma_q->udma->name, udma_q->qid,
421 al_err("udma [%s %d]: %s timeout waiting for dcp==crhp\n",
422 udma_q->udma->name, udma_q->qid, __func__);
427 if (udma_q->udma->type == UDMA_TX)
440 int al_udma_q_handle_get(struct al_udma *udma, uint32_t qid,
444 al_assert(udma);
447 if (unlikely(qid >= udma->num_of_queues)) {
448 al_err("udma [%s]: invalid queue id (%d)\n", udma->name, qid);
451 *q_handle = &udma->udma_q[qid];
458 int al_udma_state_set(struct al_udma *udma, enum al_udma_state state)
462 al_assert(udma != NULL);
463 if (state == udma->state)
464 al_dbg("udma [%s]: requested state identical to "
465 "current state (%d)\n", udma->name, state);
467 al_dbg("udma [%s]: change state from (%s) to (%s)\n",
468 udma->name, al_udma_states_name[udma->state],
483 al_err("udma: invalid state (%d)\n", state);
487 if (udma->type == UDMA_TX)
488 al_reg_write32(&udma->udma_regs->m2s.m2s.change_state, reg);
490 al_reg_write32(&udma->udma_regs->s2m.s2m.change_state, reg);
492 udma->state = state;
499 enum al_udma_state al_udma_state_get(struct al_udma *udma)
507 if (udma->type == UDMA_TX)
508 state_reg = al_reg_read32(&udma->udma_regs->m2s.m2s.state);
510 state_reg = al_reg_read32(&udma->udma_regs->s2m.s2m.state);
595 al_dbg("udma [%s %d]: packet completed. first desc %p (ixd 0x%x)"
596 " descs %d\n", udma_q->udma->name, udma_q->qid, *cdesc,