Lines Matching refs:spi
627 SCSI_XPT_XPORT(spi, SPI);
1058 struct ccb_trans_settings_spi *spi;
1078 spi = &cts.xport_specific.spi;
1083 if ((spi->valid & CTS_SPI_VALID_SYNC_RATE) == 0) {
1100 if ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) == 0
1101 || spi->sync_offset == 0 || spi->sync_period == 0) {
1122 spi->valid = CTS_SPI_VALID_SYNC_RATE | CTS_SPI_VALID_SYNC_OFFSET;
1124 spi->sync_period++;
1125 if (spi->sync_period >= 0xf) {
1126 spi->sync_period = 0;
1127 spi->sync_offset = 0;
1137 ("DV: period 0x%x\n", spi->sync_period));
1138 printf("setting period to 0x%x\n", spi->sync_period);
1147 ("DV: failed to set period 0x%x\n", spi->sync_period));
1148 if (spi->sync_period == 0) {
2776 struct ccb_trans_settings_spi *spi;
2779 spi = &cts->xport_specific.spi;
2781 cur_spi = &cur_cts.xport_specific.spi;
2784 if ((spi->valid & CTS_SPI_VALID_SYNC_RATE) == 0)
2785 spi->sync_period = cur_spi->sync_period;
2787 spi->sync_period = 0;
2788 if ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) == 0)
2789 spi->sync_offset = cur_spi->sync_offset;
2791 spi->sync_offset = 0;
2792 if ((spi->valid & CTS_SPI_VALID_PPR_OPTIONS) == 0)
2793 spi->ppr_options = cur_spi->ppr_options;
2795 spi->ppr_options = 0;
2796 if ((spi->valid & CTS_SPI_VALID_BUS_WIDTH) == 0)
2797 spi->bus_width = cur_spi->bus_width;
2799 spi->bus_width = 0;
2800 if ((spi->valid & CTS_SPI_VALID_DISC) == 0) {
2801 spi->flags &= ~CTS_SPI_FLAGS_DISC_ENB;
2802 spi->flags |= cur_spi->flags & CTS_SPI_FLAGS_DISC_ENB;
2805 spi->flags &= ~CTS_SPI_FLAGS_DISC_ENB;
2811 spi->sync_period = 0;
2812 spi->sync_offset = 0;
2815 switch (spi->bus_width) {
2828 spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
2835 spi->bus_width = MSG_EXT_WDTR_BUS_8_BIT;
2839 spi3caps = cpi.xport_specific.spi.ppr_options;
2845 spi->ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2848 spi->ppr_options &= ~MSG_EXT_PPR_IU_REQ;
2851 spi->ppr_options &= ~MSG_EXT_PPR_QAS_REQ;
2854 if (spi->bus_width == 0)
2855 spi->ppr_options = 0;
2857 if ((spi->valid & CTS_SPI_VALID_DISC)
2858 && ((spi->flags & CTS_SPI_FLAGS_DISC_ENB) == 0)) {
2875 && (spi->flags & (CTS_SPI_VALID_SYNC_RATE|
3056 struct ccb_trans_settings_spi *spi =
3057 &cts->xport_specific.spi;
3059 if ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) != 0
3060 && spi->sync_offset != 0) {
3061 *freq = scsi_calc_syncsrate(spi->sync_period);
3064 if ((spi->valid & CTS_SPI_VALID_BUS_WIDTH) != 0)
3065 *speed *= (0x01 << spi->bus_width);
3103 struct ccb_trans_settings_spi *spi;
3105 spi = &cts.xport_specific.spi;
3109 (spi->ppr_options & MSG_EXT_PPR_DT_REQ) != 0
3111 spi->sync_offset);
3113 if ((spi->valid & CTS_SPI_VALID_BUS_WIDTH) != 0
3114 && spi->bus_width > 0) {
3120 sbuf_printf(sb, "%dbit)", 8 * (0x01 << spi->bus_width));
3159 struct ccb_trans_settings_spi *spi;
3161 spi = &cts.xport_specific.spi;
3165 (spi->ppr_options & MSG_EXT_PPR_DT_REQ) != 0
3167 spi->sync_offset);
3169 if ((spi->valid & CTS_SPI_VALID_BUS_WIDTH) != 0
3170 && spi->bus_width > 0) {
3176 printf("%dbit)", 8 * (0x01 << spi->bus_width));