Lines Matching refs:COMP
823 COMP(0, "clk_cs", cs_p, 0,
827 COMP(0, "clk_cci_trace_c", cci_trace_p, 0,
829 COMP(0, "aclk_cci_pre_c", aclk_cci_p, 0,
833 COMP(0, "pclk_ddr_c", pll_src_cpll_gpll_p, 0,
835 COMP(SCLK_DDRC, "clk_ddrc", ddrclk_p, 0,
841 COMP(0, "aclk_vcodec_pre_c", pll_src_cpll_gpll_npll_ppll_p, 0,
847 COMP(0, "aclk_vdu_pre_c", pll_src_cpll_gpll_npll_ppll_p, 0,
851 COMP(0, "clk_vdu_ca_c", pll_src_cpll_gpll_npll_npll_p, 0,
853 COMP(0, "clk_vdu_core_c", pll_src_cpll_gpll_npll_npll_p, 0,
859 COMP(0, "aclk_iep_pre_c", pll_src_cpll_gpll_npll_ppll_p, 0,
865 COMP(0, "aclk_rga_pre_c", pll_src_cpll_gpll_npll_ppll_p, 0,
869 COMP(0, "aclk_center_c", pll_src_cpll_gpll_npll_npll_p, 0,
871 COMP(SCLK_RGA_CORE, "clk_rga_core_c", pll_src_cpll_gpll_npll_ppll_p, 0,
875 COMP(0, "hclk_sd_c", pll_src_cpll_gpll_p, 0,
877 COMP(0, "aclk_gpu_pre_c", pll_src_ppll_cpll_gpll_npll_upll_p, 0,
889 COMP(0, "aclk_perihp_c", aclk_perihp_p, 0,
893 COMP(0, "clk_sdio_c", pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
897 COMP(0, "clk_sdmmc_c", pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
901 COMP(0, "clk_pcie_pm_c", pll_src_cpll_gpll_npll_24m_p, 0,
911 COMP(0, "clk_pcie_core_cru_c", pll_src_cpll_gpll_npll_npll_p, 0,
923 COMP(0, "clk_gmac_c", pll_src_cpll_gpll_npll_npll_p, 0,
925 COMP(0, "aclk_gmac_pre_c", aclk_gmac_p, 0,
929 COMP(ACLK_EMMC, "aclk_emmc", aclk_emmc_p, 0,
933 COMP(0, "clk_emmc_c", pll_src_cpll_gpll_npll_upll_24m_p, 0,
941 COMP(0, "aclk_perilp0_c", aclk_perilp0_p, 0,
945 COMP(0, "fclk_cm0s_c", fclk_cm0s_p, 0,
947 COMP(0, "clk_crypto0_c", pll_src_cpll_gpll_ppll_p, 0,
953 COMP(HCLK_PERILP1, "hclk_perilp1", hclk_perilp1_p, 0,
959 COMP(0, "clk_crypto1_c", pll_src_cpll_gpll_ppll_p, 0,
963 COMP(0, "clk_tsadc_c", pll_src_p, 0,
969 COMP(0, "clk_i2s0_div_c", pll_src_cpll_gpll_p, 0,
975 COMP(0, "clk_i2s1_div_c", pll_src_cpll_gpll_p, 0,
981 COMP(0, "clk_i2s2_div_c", pll_src_cpll_gpll_p, 0,
991 COMP(0, "clk_spdif_rec_dptx_c", pll_src_cpll_gpll_p, 0,
995 COMP(0, "clk_spdif_div_c", pll_src_cpll_gpll_p, 0,
1032 COMP(0, "clk_testout2_c", clk_testout2_p, 0,
1036 COMP(0, "clk_testout1_c", clk_testout1_p, 0,
1040 COMP(0, "aclk_usb3_c", pll_src_cpll_gpll_npll_npll_p, 0,
1044 COMP(0, "clk_usb3otg0_suspend_c", pll_src_p, 0,
1048 COMP(0, "clk_usb3otg1_suspend_c", pll_src_p, 0,
1052 COMP(0, "aclk_hdcp_c", pll_src_cpll_gpll_ppll_p, 0,
1054 COMP(0, "aclk_vio_c", pll_src_cpll_gpll_ppll_p, 0,
1066 COMP(0, "pclk_edp_c", pll_src_cpll_gpll_p, 0,
1070 COMP(0, "clk_hdmi_cec_c", pll_src_p, 0,
1074 COMP(0, "clk_dp_core_c", pll_src_npll_cpll_gpll_p, 0,
1080 COMP(0, "aclk_vop0_pre_c", pll_src_vpll_cpll_gpll_npll_p, 0,
1086 COMP(0, "aclk_vop1_pre_c", pll_src_vpll_cpll_gpll_npll_p, 0,
1092 COMP(0, "dclk_vop0_div_c", pll_src_vpll_cpll_gpll_gpll_p, 0,
1098 COMP(0, "dclk_vop1_div_c", pll_src_vpll_cpll_gpll_gpll_p, 0,
1102 COMP(0, "clk_vop0_pwm_c", pll_src_vpll_cpll_gpll_gpll_p, 0,
1106 COMP(0, "clk_vop1_pwm_c", pll_src_vpll_cpll_gpll_gpll_p, 0,
1112 COMP(0, "aclk_isp0_c", pll_src_cpll_gpll_ppll_p, 0,
1118 COMP(0, "aclk_isp1_c", pll_src_cpll_gpll_ppll_p, 0,
1122 COMP(0, "clk_isp1_c", pll_src_cpll_gpll_npll_npll_p, 0,
1124 COMP(0, "clk_isp0_c", pll_src_cpll_gpll_npll_npll_p, 0,
1128 COMP(0, "aclk_gic_pre_c", pll_src_cpll_gpll_p, 0,
1132 COMP(SCLK_CIF_OUT, "clk_cifout", clk_cif_p, 0,
1142 COMP(0, "clk_spi5_c", pll_src_cpll_gpll_p, 0,
1150 COMP(0, "clk_spi1_c", pll_src_cpll_gpll_p, 0,
1152 COMP(0, "clk_spi0_c", pll_src_cpll_gpll_p, 0,
1156 COMP(0, "clk_spi4_c", pll_src_cpll_gpll_p, 0,
1158 COMP(0, "clk_spi2_c", pll_src_cpll_gpll_p, 0,
1162 COMP(0, "clk_i2c5_c", pll_src_cpll_gpll_p, 0,
1164 COMP(0, "clk_i2c1_c", pll_src_cpll_gpll_p, 0,
1168 COMP(0, "clk_i2c6_c", pll_src_cpll_gpll_p, 0,
1170 COMP(0, "clk_i2c2_c", pll_src_cpll_gpll_p, 0,
1174 COMP(0, "clk_i2c7_c", pll_src_cpll_gpll_p, 0,
1176 COMP(0, "clk_i2c3_c", pll_src_cpll_gpll_p, 0,
1180 COMP(0, "clk_uphy0_tcpdphy_ref_c", pll_src_p, 0,
1182 COMP(0, "clk_uphy0_tcpdcore_c", pll_src_24m_32k_cpll_gpll_p, 0,
1186 COMP(0, "clk_uphy1_tcpdphy_ref_c", pll_src_p, 0,
1188 COMP(0, "clk_uphy1_tcpdcore_c", pll_src_24m_32k_cpll_gpll_p, 0,