Lines Matching defs:div1
218 int div0, div1;
226 for (div1 = 1; div1 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX; div1++) {
227 div0 = (io_pll_frequency + div1 * frequency / 2) /
228 div1 / frequency;
230 ((io_pll_frequency / div0 / div1) + 500) / 1000 ==
235 if (div1 > ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX)
245 (div1 << ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_SHIFT) |
319 int div0, div1;
348 for (div1 = 1; div1 <= ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX; div1++) {
349 div0 = (base_frequency + div1 * frequency / 2) /
350 div1 / frequency;
352 ((base_frequency / div0 / div1) + 500) / 1000 ==
357 if (div1 > ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX)
369 reg |= (div1 << ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_SHIFT) |
378 return (base_frequency / div0 / div1);
385 int div0, div1;
416 div1 = (reg & ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK) >>
426 if (div1 == 0)
427 div1 = 1;
429 frequency = (base_frequency / div0 / div1);