arm/ti/ti_sdma.c

167  *	ti_sdma_write_4 - writes a 32-bit value to one of the DMA registers
176 ti_sdma_write_4(struct ti_sdma_softc *sc, bus_size_t off, uint32_t val)
276 				ti_sdma_write_4(sc, DMA4_CSR(ch), DMA4_CSR_CLEAR_MASK);
277 				ti_sdma_write_4(sc, DMA4_IRQSTATUS_L(j), (1 << ch));
382 		ti_sdma_write_4(sc, addr, 0x00000000);
424 	ti_sdma_write_4(sc, DMA4_CICR(ch), 0);
427 	ti_sdma_write_4(sc, DMA4_CCR(ch), 0);
430 	ti_sdma_write_4(sc, DMA4_CSR(ch), DMA4_CSR_CLEAR_MASK);
432 		ti_sdma_write_4(sc, DMA4_IRQSTATUS_L(j), (1 << ch));
437 		ti_sdma_write_4(sc, addr, 0x00000000);
476 	ti_sdma_write_4(sc, DMA4_CICR(ch), 0x0000);
483 		ti_sdma_write_4(sc, DMA4_IRQENABLE_L(j), irq_enable);
539 	ti_sdma_write_4(sc, DMA4_CICR(ch), flags);
545 	ti_sdma_write_4(sc, DMA4_IRQENABLE_L(0), irq_enable);
647 	ti_sdma_write_4(sc, DMA4_CSDP(ch),
651 	ti_sdma_write_4(sc, DMA4_CEN(ch), elmcnt);
654 	ti_sdma_write_4(sc, DMA4_CFN(ch), frmcnt);
657 	ti_sdma_write_4(sc, DMA4_CSSA(ch), src_paddr);
658 	ti_sdma_write_4(sc, DMA4_CDSA(ch), dst_paddr);
661 	ti_sdma_write_4(sc, DMA4_CCR(ch), channel->reg_ccr);
664 	ti_sdma_write_4(sc, DMA4_CSE(ch), 0x0001);
667 	ti_sdma_write_4(sc, DMA4_CSF(ch), 0x0001);
670 	ti_sdma_write_4(sc, DMA4_CDE(ch), 0x0001);
673 	ti_sdma_write_4(sc, DMA4_CDF(ch), 0x0001);
676 	ti_sdma_write_4(sc, DMA4_CSR(ch), 0x1FFE);
681 	ti_sdma_write_4(sc, DMA4_CCR(ch), ccr);
742 		ti_sdma_write_4(sc, DMA4_CSDP(ch),
746 	ti_sdma_write_4(sc, DMA4_CEN(ch), elmcnt);
749 	ti_sdma_write_4(sc, DMA4_CFN(ch), frmcnt);
752 	ti_sdma_write_4(sc, DMA4_CSSA(ch), src_paddr);
753 	ti_sdma_write_4(sc, DMA4_CDSA(ch), dst_paddr);
756 	ti_sdma_write_4(sc, DMA4_CCR(ch),
760 	ti_sdma_write_4(sc, DMA4_CSE(ch), 0x0001);
764 		ti_sdma_write_4(sc, DMA4_CSF(ch), pktsize);
766 		ti_sdma_write_4(sc, DMA4_CDF(ch), pktsize);
769 	ti_sdma_write_4(sc, DMA4_CDE(ch), 0x0001);
772 	ti_sdma_write_4(sc, DMA4_CSR(ch), 0x1FFE);
777 	ti_sdma_write_4(sc, DMA4_CCR(ch), ccr);
817 	ti_sdma_write_4(sc, DMA4_CICR(ch), 0);
820 	ti_sdma_write_4(sc, DMA4_CCR(ch), 0);
823 	ti_sdma_write_4(sc, DMA4_CSR(ch), DMA4_CSR_CLEAR_MASK);
825 		ti_sdma_write_4(sc, DMA4_IRQSTATUS_L(j), (1 << ch));
1190 		ti_sdma_write_4(sc, DMA4_IRQENABLE_L(i), 0x00000000);
1196 		ti_sdma_write_4(sc, DMA4_OCP_SYSCONFIG, 0x0002);