arm/ti/ti_sdma.c

127 	struct ti_sdma_channel sc_channel[NUM_DMA_CHANNELS];
236 				channel = &sc->sc_channel[ch];
350 	channel = &sc->sc_channel[*ch];
475 	sc->sc_channel[ch].reg_cicr = 0x0000;
487 	sc->sc_channel[ch].need_reg_write = 1;
536 	sc->sc_channel[ch].reg_cicr = flags;
548 	sc->sc_channel[ch].need_reg_write = 1;
644 	channel = &sc->sc_channel[ch];
738 	channel = &sc->sc_channel[ch];
829 	sc->sc_channel[ch].need_reg_write = 1;
865 	sc->sc_channel[ch].reg_csdp &= ~DMA4_CSDP_SRC_ENDIANISM(1);
866 	sc->sc_channel[ch].reg_csdp |= DMA4_CSDP_SRC_ENDIANISM(src);
868 	sc->sc_channel[ch].reg_csdp &= ~DMA4_CSDP_DST_ENDIANISM(1);
869 	sc->sc_channel[ch].reg_csdp |= DMA4_CSDP_DST_ENDIANISM(dst);
871 	sc->sc_channel[ch].need_reg_write = 1;
910 	sc->sc_channel[ch].reg_csdp &= ~DMA4_CSDP_SRC_BURST_MODE(0x3);
911 	sc->sc_channel[ch].reg_csdp |= DMA4_CSDP_SRC_BURST_MODE(src);
913 	sc->sc_channel[ch].reg_csdp &= ~DMA4_CSDP_DST_BURST_MODE(0x3);
914 	sc->sc_channel[ch].reg_csdp |= DMA4_CSDP_DST_BURST_MODE(dst);
916 	sc->sc_channel[ch].need_reg_write = 1;
952 	sc->sc_channel[ch].reg_csdp &= ~DMA4_CSDP_DATA_TYPE(0x3);
953 	sc->sc_channel[ch].reg_csdp |= DMA4_CSDP_DATA_TYPE(type);
955 	sc->sc_channel[ch].need_reg_write = 1;
992 	sc->sc_channel[ch].callback = callback;
993 	sc->sc_channel[ch].callback_data = data;
995 	sc->sc_channel[ch].need_reg_write = 1;
1036 	ccr = sc->sc_channel[ch].reg_ccr;
1056 	sc->sc_channel[ch].reg_ccr = ccr;
1058 	sc->sc_channel[ch].need_reg_write = 1;
1100 	ccr = sc->sc_channel[ch].reg_ccr;
1108 	sc->sc_channel[ch].reg_ccr = ccr;
1110 	sc->sc_channel[ch].need_reg_write = 1;