Lines Matching refs:ADC_WRITE4
114 ADC_WRITE4(sc, ADC_IRQENABLE_SET,
136 ADC_WRITE4(sc, ADC_CTRL, reg);
153 ADC_WRITE4(sc, ADC_STEPENABLE, 0);
156 ADC_WRITE4(sc, ADC_CTRL, ADC_READ4(sc, ADC_CTRL) & ~ADC_CTRL_ENABLE);
159 ADC_WRITE4(sc, ADC_IRQENABLE_CLR,
163 ADC_WRITE4(sc, ADC_IRQSTATUS, ADC_READ4(sc, ADC_IRQSTATUS));
202 ADC_WRITE4(sc, ADC_STEPENABLE, enabled);
241 ADC_WRITE4(sc, reg, val);
289 ADC_WRITE4(sc, ADC_CLKDIV, reg);
352 ADC_WRITE4(sc, input->stepdelay, reg & ADC_STEP_OPEN_DELAY);
516 ADC_WRITE4(sc, ADC_IRQENABLE_CLR,
539 ADC_WRITE4(sc, ADC_IRQSTATUS, status);
639 ADC_WRITE4(sc, ADC_STEPCFG(i), stepconfig);
640 ADC_WRITE4(sc, ADC_STEPDLY(i), STEPDLY_OPEN);
658 ADC_WRITE4(sc, ADC_STEPCFG(i), stepconfig);
659 ADC_WRITE4(sc, ADC_STEPDLY(i), STEPDLY_OPEN);
664 ADC_WRITE4(sc, ADC_TC_CHARGE_STEPCONFIG, val);
665 ADC_WRITE4(sc, ADC_TC_CHARGE_DELAY, sc->sc_charge_delay);
673 ADC_WRITE4(sc, ADC_STEPCFG(start_step), stepconfig);
674 ADC_WRITE4(sc, ADC_STEPDLY(start_step), STEPDLY_OPEN);
677 ADC_WRITE4(sc, ADC_STEPCFG(start_step), stepconfig);
678 ADC_WRITE4(sc, ADC_STEPDLY(start_step), STEPDLY_OPEN);
680 ADC_WRITE4(sc, ADC_FIFO1THRESHOLD, (sc->sc_coord_readouts*2 + 2) - 1);
699 ADC_WRITE4(sc, ADC_IDLECONFIG, val);
859 ADC_WRITE4(sc, ADC_CTRL, reg | ADC_CTRL_STEP_WP | ADC_CTRL_STEP_ID);
867 ADC_WRITE4(sc, ADC_CLKDIV, 24 - 1);
869 ADC_WRITE4(sc, ADC_CLKDIV, 2400 - 1);